Rolf Drechsler - researchr alias

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Viewing Publication 1 - 100 from 936

2025

FARAD: Automated Formal Verification of Approximate Restoring Array DividersChandan Kumar Jha 0001, Khushboo Qayyum, Muhammad Hassan 0001, Rolf Drechsler. vlsid 2025: 43-48 [doi]

Correct and Verify - CAV: Exploiting Binary Decision Diagrams to Enable Formal Verification of Approximate Adders With Correct Carry BitsChandan Kumar Jha 0001, Khushboo Qayyum, Muhammad Hassan 0002, Rolf Drechsler. tcasI, 72(4):1718-1730, April 2025. [doi]

Preserving and Improving Verifiability of Circuits Based on Local TransformationsRolf Drechsler. latw 2025: 1-2 [doi]

Lower bound proof for the size of BDDs representing a shifted additionJan Kleinekathöfer, Alireza Mahzoon, Rolf Drechsler. ipl, 190:106571, 2025. [doi]

Polynomial Formal Verification of Multi-Valued Approximate Circuits Within Constant CutwidthMohamed A. Nadeem, Chandan Kumar Jha 0001, Rolf Drechsler. tcasI, 72(3):1411-1424, March 2025. [doi]

True-PolyTronik: Securing Circuits Against Laser Logic State Imaging Attack Using RFETSajjad Parvin, Chandan Kumar Jha 0001, Frank Sill Torres, Rolf Drechsler. vlsid 2025: 37-42 [doi]

OPTI-Sim: Performing Optical Probing Simulation on Layout Design FilesSajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler. tcad, 44(4):1553-1566, April 2025. [doi]

2024

Input Distribution Aware Library of Approximate Adders Based on Memristor-Aided LogicChandan Kumar Jha 0001, Sallar Ahmadi-Pour, Rolf Drechsler. vlsid 2024: 577-582 [doi]

EnR: extend and reduce methodology to enable formal verification of truncated addersChandan Kumar Jha 0001, Khushboo Qayyum, Muhammad Hassan 0001, Rolf Drechsler. it, 66(4-5):124-136, 2024. [doi]

cecApprox: Enabling Automated Combinational Equivalence Checking for Approximate CircuitsChandan Kumar Jha 0001, Muhammad Hassan 0002, Rolf Drechsler. tcasI, 71(7):3282-3293, July 2024. [doi]

veriSIMPLER: An Automated Formal Verification Methodology for SIMPLER MAGIC Design Style Based In-Memory ComputingChandan Kumar Jha 0001, Khushboo Qayyum, Kemal Çaglar Coskun, Simranjeet Singh, Muhammad Hassan 0002, Rainer Leupers, Farhad Merchant, Rolf Drechsler. tcasI, 71(9):4169-4179, September 2024. [doi]

LLM-Guided Formal Verification Coupled with Mutation TestingMuhammad Hassan 0002, Sallar Ahmadi-Pour, Khushboo Qayyum, Chandan Kumar Jha 0001, Rolf Drechsler. date 2024: 1-2 [doi]

Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar ArrayAnkit Bende, Simranjeet Singh, Chandan Kumar Jha 0001, Tim Kempen, Felix Cüppers, Christopher Bengel, Andre Zambanini, Dennis Nielinger, Sachin B. Patkar, Rolf Drechsler, Rainer Waser, Farhad Merchant, Vikas Rana. vlsid 2024: 565-570 [doi]

EvoAl - Codeless Domain-OptimisationBernhard Johannes Berger, Christina Plump, Lauren Paul, Rolf Drechsler. gecco 2024: 1640-1648 [doi]

Why less is sometimes more: Using Boolean literals to solve 2048Bernhard J. Berger, Christina Plump, Rolf Drechsler. it, 66(4-5):174-186, 2024. [doi]

ReSG: A Data Structure for Verification of Majority-based In-memory Computing on ReRAM CrossbarsKousik Bhunia, Arighna Deb, Kamalika Datta, Muhammad Hassan 0002, Saeideh Shirinzadeh, Rolf Drechsler. tecs, 23(6), November 2024. [doi]

Security Coverage Metrics for Information Flow at the System LevelEce Nur Demirhan Coskun, Sallar Ahmadi-Pour, Muhammad Hassan 0002, Rolf Drechsler. aspdac 2024: 945-950 [doi]

Polynomial Formal Verification of Sequential CircuitsCaroline Dominik, Rolf Drechsler. date 2024: 1-6 [doi]

The Future is Hybrid: Next Generation Data Structures for Formal VerificationRolf Drechsler, Christina Plump, Martha Schnieber. ats 2024: 1-6 [doi]

Solving Boolean Problems and BeyondRolf Drechsler, Görschwin Fey. it, 66(4-5):91, 2024. [doi]

Early SoCs Information Flow Policies Validation Using SystemC-Based Virtual Prototypes at the ESLMehran Goli, Rolf Drechsler. tecs, 23(5), September 2024. [doi]

A Multi-Objective Evolutionary Approach for Test Network DesignPayam Habiby, Fatemeh Shirinzadeh, Sebastian Huhn 0001, Rolf Drechsler. ets 2024: 1-4 [doi]

Is Simulation the only Alternative for Effective Verification of Dynamic Quantum Circuits?Liam Hurwitz, Kamalika Datta, Abhoy Kole, Rolf Drechsler. RC 2024: 201-217 [doi]

Determining the Effect of Feedback Quality on User Engagement on Online Idea Crowdsourcing Platforms Using an AI modelSana Hassan Imam, Christopher A. Metz, Lars Hornuf, Rolf Drechsler. pacmhci, 8(CSCW2):1-26, 2024. [doi]

Processor Vulnerability Detection with the Aid of Assertions: RISC-V Case StudyMohammad Reza Heidari Iman, Sallar Ahmadi-Pour, Rolf Drechsler, Tara Ghasempouri. norcas 2024: 1-7 [doi]

Design Automation Challenges and Benefits of Dynamic Quantum Circuit in Present NISQ Era and Beyond: (Invited Paper)Abhoy Kole, Kamalika Datta, Rolf Drechsler. isvlsi 2024: 601-606 [doi]

Dynamic Realization of Multiple Control Toffoli GateAbhoy Kole, Arighna Deb, Kamalika Datta, Rolf Drechsler. date 2024: 1-6 [doi]

Exploring the Potential of Dynamic Quantum Circuit for Improving Device ScalabilityAbhoy Kole, Kamalika Datta, Rolf Drechsler. socc 2024: 1-5 [doi]

Exploiting the Extended Neighborhood of Hexagonal Qubit Architecture for Mapping Quantum CircuitsAbhoy Kole, Kamalika Datta, Indranil Sengupta 0001, Rolf Drechsler. jetc, 20(4), October 2024. [doi]

Polynomial Formal Verification of Arithmetic CircuitsAlireza Mahzoon, Rolf Drechsler. fteda, 14(3):171-244, 2024. [doi]

SAT can Ensure Polynomial Bounds for the Verification of Circuits with Limited CutwidthLuca Müller, Rolf Drechsler. dsd 2024: 57-64 [doi]

Polynomial Formal Verification of Multi-Valued Logic Circuits within Constant Cutwidth ArchitecturesMohamed A. Nadeem, Rolf Drechsler. ismvl 2024: 149-154 [doi]

Polynomial Formal Verification of Approximate Adders with Constant CutwidthMohamed Nadeem, Chandan Kumar Jha 0001, Rolf Drechsler. ets 2024: 1-6 [doi]

Hidden Cost of Circuit Design with RFETsSajjad Parvin, Chandan Kumar Jha 0001, Frank Sill Torres, Rolf Drechsler. date 2024: 1-2 [doi]

Lower the RISC: Designing optical-probing-attack-resistant coresSajjad Parvin, Sallar Ahmadi-Pour, Chandan Kumar Jha 0001, Frank Sill Torres, Rolf Drechsler. mam, 111:105121, 2024. [doi]

Aufbau einer überregionalen Data-Science-CommunityHelen Pfuhl, Lena Steinmann, Dirk Nowotka, Rolf Drechsler. gi 2024: 2197-2203 [doi]

Finding the perfect MRI sequence for your patient - Towards an optimisation workflow for MRI-sequencesChristina Plump, Daniel Christopher Hoinkiss, Jörn Huber, Bernhard J. Berger, Matthias Günther, Christoph Lüth, Rolf Drechsler. cec 2024: 1-9 [doi]

LLMs for Hardware Verification: Frameworks, Techniques, and Future DirectionsKhushboo Qayyum, Sallar Ahmadi-Pour, Chandan Kumar Jha 0001, Muhammad Hassan 0002, Rolf Drechsler. ats 2024: 1-6 [doi]

Late Breaking Results: LLM-assisted Automated Incremental Proof Generation for Hardware VerificationKhushboo Qayyum, Muhammad Hassan 0002, Sallar Ahmadi-Pour, Chandan Kumar Jha 0001, Rolf Drechsler. dac 2024: [doi]

Exploring the Potential of Decision Diagrams for Efficient In-Memory Design VerificationKhushboo Qayyum, Abhoy Kole, Kamalika Datta, Muhammad Hassan 0002, Rolf Drechsler. glvlsi 2024: 502-506 [doi]

AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL DesignRuidi Qiu, Grace Li Zhang, Rolf Drechsler, Ulf Schlichtmann, Bing Li 0005. mlcad 2024: [doi]

Towards Formal Verification for MAC-based In-Memory ComputingFatemeh Shirinzadeh, Kamalika Datta, Saeideh Shirinzadeh, Abhoy Kole, Rolf Drechsler. ats 2024: 1-6 [doi]

In-Memory Mirroring: Cloning Without ReadingSimranjeet Singh, Ankit Bende, Chandan Kumar Jha 0001, Vikas Rana, Rolf Drechsler, Sachin B. Patkar, Farhad Merchant. vlsi 2024: 1-6 [doi]

MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-MemorySimranjeet Singh, Chandan Kumar Jha 0001, Ankit Bende, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant. aspdac 2024: 282-287 [doi]

Complete and Efficient Verification for a RISC-V Processor Using Formal VerificationLennart Weingarten, Kamalika Datta, Abhoy Kole, Rolf Drechsler. date 2024: 1-6 [doi]

Improving Self-Fault-Tolerance Capability of Memristor Crossbar Using a Weight-Sharing ApproachDev Narayan Yadav, Phrangboklang Lyngton Thangkhiew, F. Lalchhandama, Kamalika Datta, Rolf Drechsler, Indranil Sengupta 0001. ats 2024: 1-6 [doi]

Improving Virtual Prototype Driven Hardware Optimization by Merging Instruction SequencesJan Zielasko, Rune Krauss, Marcel Merten, Rolf Drechsler. ddecs 2024: 73-78 [doi]

Efficient Equivalence Checking of Nonlinear Analog Circuits using Gradient AscentKemal Çaglar Coskun, Muhammad Hassan 0002, Lars Hedrich, Rolf Drechsler. dac 2024: [doi]

2023

Benchmarking Multiplier Architectures for MAGIC Based In-Memory ComputingChandan Kumar Jha 0001, Rolf Drechsler. newcas 2023: 1-5 [doi]

MARADIV: Library of MAGIC-Based Approximate Restoring Array Divider Benchmark Circuits for In-Memory Computing Using MemristorsChandan Kumar Jha 0001, Sallar Ahmadi-Pour, Rolf Drechsler. tcasII, 70(7):2635-2639, July 2023. [doi]

Processor Verification using Symbolic Execution: A RISC-V Case-StudyNiklas Bruns, Vladimir Herdt, Rolf Drechsler. date 2023: 1-6 [doi]

VAST: Validation of VP-based Heterogeneous Systems against Availability Security Properties using Static Information Flow TrackingEce Nur Demirhan Coskun, Muhammad Hassan 0002, Mehran Goli, Rolf Drechsler. isqed 2023: 1-8 [doi]

Memristors: Device Modeling, Design and VerificationKamalika Datta, Rolf Drechsler. ifip5-5 2023: 254-259 [doi]

Improved Cost-Metric for Nearest Neighbor Mapping of Quantum Circuits to 2-Dimensional Hexagonal ArchitectureKamalika Datta, Abhoy Kole, Indranil Sengupta 0001, Rolf Drechsler. RC 2023: 218-231 [doi]

Verification of In-Memory Logic Design using ReRAM CrossbarsKamalika Datta, Arighna Deb, Fatemeh Shirinzadeh, Abhoy Kole, Saeideh Shirinzadeh, Rolf Drechsler. newcas 2023: 1-5 [doi]

Impact of sneak paths on in-memory logic design in memristive crossbarsKamalika Datta, Arighna Deb, Abhoy Kole, Rolf Drechsler. it, 65(1-2):29-39, May 2023. [doi]

Automated Equivalence Checking Method for Majority Based In-Memory Computing on ReRAM CrossbarsArighna Deb, Kamalika Datta, Muhammad Hassan 0002, Saeideh Shirinzadeh, Rolf Drechsler. aspdac 2023: 19-25 [doi]

Automated Polynomial Formal Verification: Human-Readable Proof GenerationRolf Drechsler, Martha Schnieber. ifip5-5 2023: 1-3 [doi]

Towards Polynomial Formal Verification of AI-Generated Arithmetic CircuitsRolf Drechsler, Alireza Mahzoon. isdcs 2023: 1-4 [doi]

Next-Generation Automatic Human-Readable Proofs Enabling Polynomial Formal VerificationRolf Drechsler, Martha Schnieber. memocode 2023: 122-125 [doi]

Divide and Verify: Using a Divide-and-Conquer Strategy for Polynomial Formal Verification of Complex CircuitsRolf Drechsler, Alireza Mahzoon. date 2023: 1-2 [doi]

Identification of ISA-Level Mutation-Classes for Qualification of RISC-V Formal VerificationMilan Funck, Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler. fdl 2023: 1-8 [doi]

RC-IJTAG: A Methodology for Designing Remotely-Controlled IEEE 1687 Scan NetworksPayam Habiby, Sebastian Huhn 0001, Rolf Drechsler. dft 2023: 1-6 [doi]

Synthesis of IJTAG Networks for Multi-Power Domain Systems on ChipsPayam Habiby, Natalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich, Sebastian Huhn 0001, Rolf Drechsler. ets 2023: 1-6 [doi]

Classifying Crowdsouring Platform Users' Engagement Behaviour using Machine Learning and XAISana Hassan Imam, Christopher A. Metz, Lars Hornuf, Rolf Drechsler. mc 2023: [doi]

Polynomial Formal Verification of Floating Point AddersJan Kleinekathöfer, Alireza Mahzoon, Rolf Drechsler. date 2023: 1-2 [doi]

Exploiting the Benefits of Clean Ancilla Based Toffoli Gate Decomposition Across ArchitecturesAbhoy Kole, Kamalika Datta, Philipp Niemann 0001, Indranil Sengupta 0001, Rolf Drechsler. RC 2023: 232-244 [doi]

Extending the Design Space of Dynamic Quantum Circuits for Toffoli based NetworkAbhoy Kole, Arighna Deb, Kamalika Datta, Rolf Drechsler. date 2023: 1-6 [doi]

Efficient Binary Decision Diagram Manipulation by Reducing the Number of Intermediate NodesRune Krauss, Mehran Goli, Rolf Drechsler. ddecs 2023: 73-78 [doi]

EDDY: A Multi-Core BDD Package with Dynamic Memory Management and Reduced FragmentationRune Krauss, Mehran Goli, Rolf Drechsler. aspdac 2023: 423-428 [doi]

Polynomial Formal Verification of Complex Circuits Using a Hybrid Proof EngineAlireza Mahzoon, Rolf Drechsler. BIRTHDAY 2023: 308-319 [doi]

Quality Assessment of Logic Locking Mechanisms using Pseudo-Boolean Optimization TechniquesMarcel Merten, Muhammad Hassan 0002, Rolf Drechsler. ddecs 2023: 105-110 [doi]

Increasing SAT-Resilience of Logic Locking Mechanisms using Formal MethodsMarcel Merten, Sebastian Huhn 0001, Rolf Drechsler. ets 2023: 1-6 [doi]

Scalable Neuroevolution of Ensemble LearnersMarcel Merten, Rune Krauss, Rolf Drechsler. gecco 2023: 667-670 [doi]

Fast and Accurate: Machine Learning Techniques for Performance Estimation of CNNs for GPGPUsChristopher A. Metz, Mehran Goli, Rolf Drechsler. ipps 2023: 754-760 [doi]

Hybrid PTX Analysis for GPU accelerated CNN inferencing aiding Computer Architecture DesignChristopher A. Metz, Christina Plump, Bernhard J. Berger, Rolf Drechsler. fdl 2023: 1-8 [doi]

Coverage-Guided Fuzzing for Plan-Based RoboticsTim Meywerk, Vladimir Herdt, Rolf Drechsler. icaart 2023: 106-114 [doi]

Polynomial Formal Verification exploiting Constant CutwidthMohamed Nadeem, Jan Kleinekathöfer, Rolf Drechsler. rsp 2023: [doi]

Lo-RISK: Design of a Low Optical Leakage and High Performance RISC-V CoreSajjad Parvin, Sallar Ahmadi-Pour, Chandan Kumar Jha 0001, Frank Sill Torres, Rolf Drechsler. coins 2023: 1-4 [doi]

Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - A RISC-V Case StudySajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler. aspdac 2023: 683-689 [doi]

FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical ProbingSajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler. date 2023: 1-2 [doi]

LAT-UP: Exposing Layout-Level Analog Hardware Trojans Using Contactless Optical ProbingSajjad Parvin, Mehran Goli, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres, Rolf Drechsler. isvlsi 2023: 1-6 [doi]

Repetitive Processes and Their Surrogate-Model Congruent Encoding for Evolutionary Algorithms - A Theoretic ProposalChristina Plump, Bernhard J. Berger, Rolf Drechsler. gecco 2023: 2289-2296 [doi]

Polynomial Formal Verification of KFDD CircuitsMartha Schnieber, Rolf Drechsler. memocode 2023: 82-89 [doi]

Finite State Automata Design using 1T1R ReRAM CrossbarSimranjeet Singh, Omar Ghazal, Chandan Kumar Jha 0001, Vikas Rana, Rolf Drechsler, Rishad A. Shafik, Alex Yakovlev, Sachin B. Patkar, Farhad Merchant. newcas 2023: 1-5 [doi]

Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design StyleSimranjeet Singh, Chandan Kumar Jha 0001, Ankit Bende, Phrangboklang Lyngton Thangkhiew, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant. esl, 15(4):230-233, December 2023. [doi]

Workshop: "Aktuelle Entwicklungen und Perspektiven (an Hochschulen) im Bereich Data Science"Lena Steinmann, Dirk Nowotka, Lea Oberländer, Helen Pfuhl, Heiner Stuckenschmidt, Rolf Drechsler. gi 2023: 73-80 [doi]

Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA ModelsSören Tempel, Tobias Brandt, Christoph Lüth, Rolf Drechsler. fdl 2023: 1-8 [doi]

Specification-Based Symbolic Execution for Stateful Network Protocol Implementations in IoTSören Tempel, Vladimir Herdt, Rolf Drechsler. iotj, 10(11):9544-9555, June 2023. [doi]

Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable TransistorsJens Trommer, N. Bhattacharjee, Thomas Mikolajick, S. Huhn, Marcel Merten, M. E. Djeridane, Muhammad Hassan 0002, Rolf Drechsler, S. Rai, N. Kavand, A. Darjani, A. Kumar, V. Sessi, M. Drescher, S. Kolodinski, M. Wiatr. date 2023: 1-6 [doi]

PolyMiR: Polynomial Formal Verification of the MicroRV32 ProcessorLennart Weingarten, Kamalika Datta, Rolf Drechsler. NANOARCH 2023: [doi]

Polynomial Formal Verification of a Processor: A RISC-V Case StudyLennart Weingarten, Alireza Mahzoon, Mehran Goli, Rolf Drechsler. isqed 2023: 1-7 [doi]

Efficient ML-Based Performance Estimation Approach Across Different Microarchitectures for RISC-V ProcessorsWeiyan Zhang, Mehran Goli, Muhammad Hassan 0002, Rolf Drechsler. dsd 2023: 693-699 [doi]

Virtual Prototype Driven Application Specific Hardware OptimizationJan Zielasko, Rolf Drechsler. fdl 2023: 1-8 [doi]

Equivalence Checking of System-Level and SPICE-Level Models of Static Nonlinear CircuitsKemal Çaglar Coskun, Muhammad Hassan 0002, Rolf Drechsler. date 2023: 1-6 [doi]

2022

Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided AgingNiklas Bruns, Vladimir Herdt, Eyck Jentzsch, Rolf Drechsler. date 2022: 1123-1126 [doi]

Unlocking High Resolution Arithmetic Operations within Memristive Crossbars for Error Tolerant ApplicationsKamalika Datta, Saman Fröhlich, Saeideh Shirinzadeh, Dev Narayan Yadav, Indranil Sengupta 0001, Rolf Drechsler. vlsi 2022: 1-6 [doi]

Virtual Prototype based Analysis of Neural Network Cache Behavior for Tiny Edge DeviceAlexander Fratzer, Vladimir Herdt, Christoph Lüth, Rolf Drechsler. fdl 2022: 1-6 [doi]

Simulation-Based Debugging of Formal Environment ModelsTim Meywerk, Arthur Niedzwiecki, Vladimir Herdt, Rolf Drechsler. med 2022: 890-895 [doi]

Toward Optical Probing Resistant Circuits: A Comparison of Logic Styles and Circuit Design TechniquesSajjad Parvin, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres, Rolf Drechsler. aspdac 2022: 429-435 [doi]

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