Leon Stok - researchr alias

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Viewing Publication 1 - 38 from 38

2023

Quantum Challenges for EDALeon Stok. ispd 2023: 196 [doi]

2021

Guest Editors' Introduction: The Resurgence of Open- Source EDA TechnologySherief Reda, Leon Stok, Pierre-Emmanuel Gaillardon. dt, 38(2):5-7, 2021. [doi]

EDA and Quantum Computing: The key role of Quantum CircuitsLeon Stok. ispd 2021: 111 [doi]

2020

EDA and Quantum Computing: a symbiotic relationship?Shesha Raghunathan, Leon Stok. dt, 37(6):71-78, 2020. [doi]

2018

Concurrent High Performance Processor Design: From Logic to PD in ParallelLeon Stok. ispd 2018: 56-57 [doi]

EDA3.0: Implications to Logic SynthesisLeon Stok. In André Inácio Reis, Rolf Drechsler, editors, Advanced Logic Synthesis. pages 1-20, Springer, 2018. [doi]

2014

The Next 25 Years in EDA: A Cloudy Future?Leon Stok. dt, 31(2):40-46, 2014. [doi]

2013

Developing Parallel EDA Tools [The Last Byte]Leon Stok. dt, 30(1):65-66, 2013. [doi]

2010

EDA challenges and options: investing for the futureRuchir Puri, William H. Joyner, Raj Jammy, Ahmed Jerraya, Jan M. Rabaey, Walden C. Rhines, Leon Stok. dac 2010: 1-2 [doi]

2009

From restrictive to prescriptive designLeon Stok. aspdac 2009: [doi]

2008

Variability and New Design ParadigmsLeon Stok. dt, 25(4):344, 2008. [doi]

2007

DAC HighlightsSachin S. Sapatnekar, Leon Stok. dt, 24(5):502-504, 2007. [doi]

2005

Minimizing power with flexible voltage islandsRuchir Puri, David S. Kung, Leon Stok. iscas 2005: 21-24 [doi]

Keeping hot chips coolRuchir Puri, Leon Stok, Subhrajit Bhattacharya. dac 2005: 285-288 [doi]

2003

2002

Layout Driven Decomposition with Congestion ConsiderationThomas Kutzschebauch, Leon Stok. date 2002: 672-676 [doi]

2001

Congestion Aware Layout Driven Logic SynthesisThomas Kutzschebauch, Leon Stok. iccad 2001: 216-223 [doi]

2000

1999

Wavefront Technology MappingLeon Stok, Andrew J. Sullivan, Mahesh A. Iyer. date 1999: 531 [doi]

1998

Gate-size selection for standard cell librariesFrederik Beeftink, Prabhakar Kudva, David S. Kung, Leon Stok. iccad 1998: 545-550 [doi]

Don t cares in synthesis: theoretical pitfalls and practical solutionsDaniel Brand, Reinaldo A. Bergamaschi, Leon Stok. tcad, 17(4):285-304, 1998. [doi]

1997

Timing analysis and optimization: from devices to systems (tutorial)Anirudh Devgan, Leon Stok, Sandip Kundu. iccad 1997: [doi]

1996

Retiming revisited and reversedGuy Even, Ilan Y. Spillinger, Leon Stok. tcad, 15(3):348-357, 1996. [doi]

BooleDozer: Logic synthesis for ASICsLeon Stok, David S. Kung, Daniel Brand, Anthony D. Drumm, Andrew J. Sullivan, Lakshmi N. Reddy, Nathaniel Hieter, David J. Geiger, Han Hsun Chao, Peter J. Osler. ibmrd, 40(4):407-430, 1996.

1995

1994

Data path synthesisLeon Stok. integration, 18(1):1-71, 1994. [doi]

Is high-level synthesis marketable? (panel)Leon Stok. isss 1994: 66 [doi]

1992

False loops through resource sharingLeon Stok. iccad 1992: 345-348 [doi]

Foreground memory management in data path synthesisLeon Stok, Jochen A. G. Jess. ijcta, 20(3):235-255, 1992. [doi]

1991

Flexible Block-Multiplier GenerationH. M. A. M. Arts, Jos T. J. van Eijndhoven, Leon Stok. iccad 1991: 106-109

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