Abstract is missing.
- Global Responsibilities in SOC DesignTaylor Scanlon. 12-13 [doi]
- On Nanoscale Integration and Gigascale Complexity in the Post.Com WorldHugo De Man. 12 [doi]
- How to Choose Semiconductor IP? - Embedded ProcessorIan Phillips. 14 [doi]
- Make Your SoC Design a Winner: Select the Right Memory IPVincent Ratford. 15 [doi]
- How to Choose Semiconductor IP: Embedded SoftwareGrant Martin. 16 [doi]
- IP Day: How to Choose Semiconductor IP?Pierre Bricaud. 17-19 [doi]
- Formal Verification of the Pentium ® 4 Floating-Point MultiplierRoope Kaivola, Naren Narasimhan. 20-27 [doi]
- Using Rewriting Rules and Positive Equality to Formally Verify Wide-Issue Out-of-Order Microprocessors with a Reorder BufferMiroslav N. Velev. 28-35 [doi]
- Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional UnitsPrabhat Mishra, Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama. 36-43 [doi]
- A Case Study for the Verification of Complex Timed Circuits: IPCMOSMarco A. Peña, Jordi Cortadella, Alexander B. Smirnov, Enric Pastor. 44-53 [doi]
- FPGA Placement by Thermodynamic Combinatorial OptimizationJuan de Vicente, Juan Lanchares, Román Hermida. 54-60 [doi]
- An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis TreesChangwen Zhuang, Yoji Kajitani, Keishi Sakanushi, Liyan Jin. 61-68 [doi]
- Arbitrary Convex and Concave Rectilinear Module Packing Using TCGJai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang. 69-77 [doi]
- A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated CircuitsMichael Pronath, Helmut E. Graeb, Kurt Antreich. 78-83 [doi]
- Exact Grading of Multiple Path Delay FaultsSaravanan Padmanaban, Spyros Tragoudas. 84-88 [doi]
- Modeling Techniques and Tests for Partial Faults in Memory DevicesZaid Al-Ars, A. J. van de Goor. 89-93 [doi]
- A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All FaultsSooryong Lee, Brad Cobb, Jennifer Dworak, Michael R. Grimaila, M. Ray Mercer. 94-101 [doi]
- Low Power Error Resilient Encoding for On-Chip Data BusesDavide Bertozzi, Luca Benini, Giovanni De Micheli. 102-109 [doi]
- Managing Power Consumption in Networks on ChipTajana Simunic, Stephen P. Boyd. 110-116 [doi]
- Competitive Analysis of Dynamic Power Management Strategies for Systems with Multiple Power Savings StatesSandy Irani, Rajesh K. Gupta, Sandeep K. Shukla. 117-123 [doi]
- AccuPower: An Accurate Power Estimation Tool for Superscalar MicroprocessorsDmitry Ponomarev, Gurhan Kucuk, Kanad Ghose. 124-131 [doi]
- IP is All About Implementation and Customer SatisfactionVernon P. Essi Jr.. 132-133 [doi]
- Using Problem Symmetry in Search Based Satisfiability AlgorithmsEvguenii I. Goldberg, Mukul R. Prasad, Robert K. Brayton. 134-141 [doi]
- BerkMin: A Fast and Robust Sat-SolverEvguenii I. Goldberg, Yakov Novikov. 142-149 [doi]
- Dynamic Scheduling and Clustering in Symbolic Image ComputationGianpiero Cabodi, Paolo Camurati, Stefano Quer. 150-157 [doi]
- Wire Placement for Crosstalk Energy Minimization in Address BusesLuca Macchiarulo, Enrico Macii, Massimo Poncino. 158-162 [doi]
- Dynamic VTH Scaling Scheme for Active Leakage Power ReductionChris H. Kim, Kaushik Roy. 163-167 [doi]
- Profile-Based Dynamic Voltage Scheduling Using Program CheckpointsAna Azevedo, Ilya Issenin, Radu Cornea, Rajesh Gupta, Nikil D. Dutt, Alexander V. Veidenbaum, Alexandru Nicolau. 168-175 [doi]
- Sizing Power/Ground Meshes for Clocking and Computing Circuit ComponentsArindam Mukherjee, Kai Wang, Lauren Hui Chen, Malgorzata Marek-Sadowska. 176-185 [doi]
- A Signature Test Framework for Rapid Production Testing of RF CircuitsRamakrishna Voorakaranam, Sasikumar Cherubal, Abhijit Chatterjee. 186-191 [doi]
- Analog IP Testing: Diagnosis and OptimizationCarlo Guardiani, Patrick McNamara, Lidia Daldoss, Sharad Saxena, Stefano Zanella, Wei Xiang, Suli Liu. 192-196 [doi]
- A New Design Flow and Testability Measure for the Generation of a Structural Test and BIST for Analogue and Mixed-Signal CircuitsChristoph Hoffmann. 197-204 [doi]
- Built-In Dynamic Current Sensor for Hard-to-Detect Faults in Mixed-Signal IcsY. Lechuga, R. Mozuelos, Mar Martínez, Salvador Bracho. 205-213 [doi]
- E-Design Based on the Reuse ParadigmL. Ghanmi, A. Ghrab, M. Hamdoun, B. Missaoui, K. Skiba, Gabriele Saucier. 214-220 [doi]
- Internet-Based Collaborative Test Generation with MOSCITOAndré Schneider, Karl-Heinz Diener, Eero Ivask, Jaan Raik, Raimund Ubar, P. Miklos, T. Cibáková, Elena Gramatová. 221-226 [doi]
- A Two-Tier Distributed Electronic Design FrameworkTom J. Kazmierski, Neil Clayton. 227-231 [doi]
- Embedded System Design Based On WebservicesAchim Rettberg, Wolfgang Thronicke. 232-237 [doi]
- Who Owns the Platform?Vassilios Gerousis, Oz Levia, Pierre G. Paulin, Mark Pinto, Chris Rowen, Gabriele Saucier. 238-239 [doi]
- IP for Embedded RobustnessMichael Nicolaidis. 240-241 [doi]
- Embedded Diagnosis IPStephen Pateras. 242-243 [doi]
- Embedded Robustness IpsEric Dupont, Michael Nicolaidis, Peter Rohr. 244-247 [doi]
- CHESMIN: A Heuristic for State Reduction in Incompletely Specified Finite State MachinesSezer Gören, F. Joel Ferguson. 248-254 [doi]
- Generalized Early Evaluation in Self-Timed CircuitsMitchell A. Thornton, Kenneth Fazel, Robert B. Reese, Cherrice Traver. 255-259 [doi]
- Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power ConstrainSeong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang. 260-267 [doi]
- A Fitting Approach to Generate Symbolic Expressions for Linear and Nonlinear Analog Circuit Performance CharacteristicsWalter Daems, Georges G. E. Gielen, Willy M. C. Sansen. 268-273 [doi]
- Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog CircuitsRolf Popp, Joerg Oehmen, Lars Hedrich, Erich Barke. 274-278 [doi]
- Constructing Symbolic Models for the Input/Output Behavior of Periodically Time-Varying Systems Using Harmonic Transfer MatricesPiet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen. 279-284 [doi]
- Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic VerificationMaciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre. 285-291 [doi]
- EDA Tools for RF: Myth or Reality?292-295 [doi]
- Dynamic Runtime Re-Scheduling Allowing Multiple Implementations of a Task for Platform-Based DesignsTin-Man Lee, Wayne Wolf, Jörg Henkel. 296-301 [doi]
- Techniques to Evolve a C++ Based System Design LanguageRobert Pasko, Serge Vernalde, Patrick Schaumont. 302-309 [doi]
- A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal EffectsAntonio J. Ginés, Eduardo J. Peralías, Adoración Rueda, Ralf Seepold, Natividad Martínez Madrid. 310-315 [doi]
- Test Structure for IC(VBE) Parameter Determination of Low Voltage ApplicationsW. Rahajandraibe, Christian Dufaza, Daniel Auvergne, B. Cialdella, B. Majoux, V. Chowdhury. 316-321 [doi]
- Global Optimization Applied to the Oscillator ProblemS. Lampe, S. Laur. 322-327 [doi]
- MEDEA+ and ITRS RoadmapsJoseph Borel, G. Matheron, Ahmed Amine Jerraya, S. Resve, M. Rogers, Wolfgang Rosenstiel, Irmtraud Rugen-Herzig, F. Theewen. 328-329 [doi]
- A Burst-Mode Oriented Back-End for the Balsa Synthesis SystemTiberiu Chelcea, Steven M. Nowick, Andrew Bardsley, Doug Edwards. 330-337 [doi]
- Detecting State Coding Conflicts in STGs Using Integer ProgrammingVictor Khomenko, Maciej Koutny, Alexandre Yakovlev. 338-345 [doi]
- Verifying Clock Schedules in the Presence of Cross TalkSoha Hassoun, Eduardo Calvillo-Gámez, Christopher Cromer. 346-351 [doi]
- Analysis of Nonlinearities in RF Front-End Architectures Using a Modified Volterra Series Approach Michaël Goffioul, Piet Wambacq, Gerd Vandersteen, Stéphane Donnay. 352-356 [doi]
- Systematic Design of a 200 Ms/S 8-bit Interpolating A/D ConverterJan Vandenbussche, Erik Lauwers, K. Uyttenhove, Michiel Steyaert, Georges G. E. Gielen. 357-361 [doi]
- Bio-Inspired Analog VLSI Design Realizes Programmable Complex Spatio-Temporal Dynamics on a Single ChipRicardo Carmona-Galán, Francisco Jiménez-Garrido, Rafael Domínguez-Castro, Servando Espejo-Meana, Ángel Rodríguez-Vázquez. 362-367 [doi]
- An Incremental Algorithm for Test Generation in Illinois Scan Architecture Based DesignsAmit R. Pandey, Janak H. Patel. 368-375 [doi]
- Gate Level Fault Diagnosis in Scan-Based BISTIsmet Bayraktaroglu, Alex Orailoglu. 376-381 [doi]
- An Interval-Based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST EnvironmentChunsheng Liu, Krishnendu Chakrabarty, Michael Gössel. 382-386 [doi]
- Reducing Test Application Time Through Test Data Mutation EncodingSherief Reda, Alex Orailoglu. 387-395 [doi]
- Hardware/Software Trade-Offs for Advanced 3G Channel CodingHeiko Michel, Alexander Worm, Norbert Wehn, Michael Münch. 396-401 [doi]
- An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAsAshok Halambi, Aviral Shrivastava, Partha Biswas, Nikil D. Dutt, Alexandru Nicolau. 402-408 [doi]
- Assigning Program and Data Objects to Scratchpad for Energy ReductionStefan Steinke, Lars Wehmeyer, Bo-Sik Lee, Peter Marwedel. 409-417 [doi]
- Networks on Chip: A New Paradigm for Systems on Chip DesignGiovanni De Micheli, Luca Benini. 418-419 [doi]
- Communication Mechanisms for Parallel DSP Systems on a ChipJoseph Williams, Nevin Heintze, Bryan D. Ackland. 420-422 [doi]
- Networks on Silicon: Combining Best-Effort and Guaranteed ServicesKees G. W. Goossens, Paul Wielage, Ad M. G. Peeters, Jef L. van Meerbergen. 423-427 [doi]
- Data Reuse Exploration Techniques for Loop-Dominated ApplicationTanja Van Achteren, Geert Deconinck, Francky Catthoor, Rudy Lauwereins. 428-535 [doi]
- EAC: A Compiler Framework for High-Level Energy Estimation and OptimizationIsmail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam. 436-442 [doi]
- Power Savings in Embedded Processors through Decode Filer CacheWeiyu Tang, Rajesh K. Gupta, Alexandru Nicolau. 443-448 [doi]
- Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded ProcessorsLuca Benini, Davide Bruni, Alberto Macii, Enrico Macii. 449-450 [doi]
- Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model Murat R. Becer, Vladimir Zolotov, David Blaauw, Rajendran Panda, Ibrahim N. Hajj. 456-464 [doi]
- Hierarchical Current Density Verification for Electromigration Analysis in Arbitrary Shaped Metallization Patterns of Analog CircuitsGoeran Jerke, Jens Lienig. 464-469 [doi]
- A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna ProblemLi-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong, I-Min Liu. 470-477 [doi]
- Test Planning and Design Space Exploration in a Core-Based EnvironmentÉrika F. Cota, Luigi Carro, Marcelo Lubaszewski, Alex Orailoglu. 478-485 [doi]
- A Hierarchical Test Scheme for System-On-Chip DesignsJin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin. 486-490 [doi]
- Efficient Wrapper/TAM Co-Optimization for Large SOCsVikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen. 491-498 [doi]
- Beyond UML to an End-of-Line Functional Test EngineAndrea Baldini, Alfredo Benso, Paolo Prinetto, Sergio Mo, Andrea Taddei. 499-505 [doi]
- Event Model Interfaces for Heterogeneous System AnalysisKai Richter, Rolf Ernst. 506-513 [doi]
- Energy-Efficient Mapping and Scheduling for DVS Enabled Distributed Embedded SystemsMarcus T. Schmitz, Bashir M. Al-Hashimi, Petru Eles. 514-521 [doi]
- A Layered, Codesign Virtual Machine Approach to Modeling Computer SystemsJoAnn M. Paul, Donald E. Thomas. 522-528 [doi]
- Automatic Evaluation of the Accuracy of Fixed-Point AlgorithmsDaniel Menard, Olivier Sentieys. 529-537 [doi]
- Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC DesignsK. Brock, C. Edwards, R. Lannoo, Ulf Schlichtmann, Antun Domic, Jacques Benkoski, David Overhauser, M. Kliment. 538-539 [doi]
- A Video Compression Case Study on a Reconfigurable VLIW ArchitectureDavide Rizzo, Osvaldo Colavin. 540-546 [doi]
- A Complete Data Scheduler for Multi-Context Reconfigurable ArchitecturesMarcos Sanchez-Elez, Milagros Fernández, Rafael Maestre, Fadi J. Kurdahi, Román Hermida, Nader Bagherzadeh. 547-552 [doi]
- Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP ApplicationsGilles Sassatelli, Lionel Torres, Pascal Benoit, Thierry Gil, Camille Diou, Gaston Cambon, Jérôme Galy. 553-558 [doi]
- (Self-)reconfigurable Finite State Machines: Theory and ImplementationJürgen Teich, Markus Köster. 559-567 [doi]
- A Linear-Centric Simulation Framework for Parametric FluctuationsEmrah Acar, Sani R. Nassif, Lawrence T. Pileggi. 568-575 [doi]
- Automatic Generation of Common-Centroid Capacitor Arrays with Arbitrary Capacitor RatioMohamed Dessouky, DiaaEldin Sayed. 576-580 [doi]
- Analog Circuit Sizing Using Adaptive Worst-Case Parameter SetsRobert Schwencker, Frank Schenkel, Michael Pronath, Helmut E. Graeb. 581-585 [doi]
- High-Frequency Nonlinear Amplifier Model for the Efficient Evaluation of Inband Distortion Under Nonlinear Load-Pull ConditionsGerd Vandersteen, Piet Wambacq, Stéphane Donnay, Frans Verbeyst. 586-591 [doi]
- Effective Software Self-Test Methodology for Processor CoresNektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian. 592-597 [doi]
- Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data CompressionAnshuman Chandra, Krishnendu Chakrabarty. 598-603 [doi]
- Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/DecompressionPaul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici. 604-611 [doi]
- Problems Due to Open Faults in the Interconnections of Self-Checking Data-PathsMichele Favalli, Cecilia Metra. 612-619 [doi]
- Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC DesignSungjoo Yoo, Gabriela Nicolescu, Lovic Gauthier, Ahmed Amine Jerraya. 620-627 [doi]
- Window-Based Susceptance Models for Large-Scale RLC Circuit AnalysesHui Zheng, Lawrence T. Pileggi, Michael W. Beattie, Byron Krauter. 628-633 [doi]
- A Linear-Centric Modeling Approach to Harmonic Balance AnalysisPeng Li, Lawrence T. Pileggi. 634-639 [doi]
- An Energy Estimation Method for Asynchronous Circuits with Application to an Asynchronous MicroprocessorPaul I. Pénzes, Alain J. Martin. 640-649 [doi]
- Design Automation for Deepsubmicron: Present and FutureRalph H. J. M. Otten, Raul Camposano, Patrick Groeneveld. 650-659 [doi]
- Reconfigurable SoC - What Will it Look Like?J. Bryan Lewis, Ivo Bolsens, Rudy Lauwereins, Chris Wheddon, Bhusan Gupta, Yankin Tanurhan. 660-663 [doi]
- Congestion-Aware Logic SynthesisDavide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas. 664-671 [doi]
- Layout Driven Decomposition with Congestion ConsiderationThomas Kutzschebauch, Leon Stok. 672-676 [doi]
- Improving Placement under the Constant Delay ModelKolja Sulimma, Wolfgang Kunz, Ingmar Neumann, Lukas VanGinneken. 677-682 [doi]
- Crosstalk Alleviation for Dynamic PLAsTzyy-Kuen Tien, Tong-Kai Tsai, Shih-Chieh Chang. 683-689 [doi]
- Flip-Flop and Repeater Insertion for Early Interconnect PlanningRuibing Lu, Guoan Zhong, Cheng-Kok Koh, Kai-Yuan Chao. 690-695 [doi]
- Congestion Estimation with Buffer Planning in Floorplan DesignWai-Chiu Wong, Chiu-Wing Sham, Evangeline F. Y. Young. 696-701 [doi]
- Maze Routing with Buffer Insertion under Transition Time ConstraintsLi-Da Huang, Minghorng Lai, D. F. Wong, Youxin Gao. 702-707 [doi]
- Optimal Transistor Tapering for High-Speed CMOS CircuitsLi Ding 0002, Pinaki Mazumder. 708-715 [doi]
- Incremental Diagnosis and Correction of Multiple Faults and ErrorsAndreas G. Veneris, Jiang Brandon Liu, Mandana Amiri, Magdy S. Abadir. 716-721 [doi]
- Test Enrichment for Path Delay Faults Using Multiple Sets of Target FaultsIrith Pomeranz, Sudhakar M. Reddy. 722-729 [doi]
- FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability AnalysisVivekananda M. Vedula, Jacob A. Abraham. 730-735 [doi]
- An Environment for Dynamic Component Composition for Efficient Co-Design Frederic Doucet, Sandeep K. Shukla, Rajesh K. Gupta, Masato Otsuka. 736-743 [doi]
- Functional Verification for SystemC Descriptions Using Constraint SolvingFabrizio Ferrandi, Michele Rendine, Donatella Sciuto. 744-751 [doi]
- The Modelling of Embedded Systems Using HASoCM. D. Edwards, P. N. Green. 752-759 [doi]
- A Functional Specification Notation for Co-Design of Mixed Analog-Digital SystemsAlex Doboli, Ranga Vemuri. 760-769 [doi]
- The Real-Time UML Standard: Definition and ApplicationBran Selic. 770-772 [doi]
- UML for Embedded Systems Specification and Design: Motivation and OverviewGrant Martin. 773-775 [doi]
- A UML-Based Design Methodology for Real-Time and Embedded SytemsGjalt G. de Jong. 776-781 [doi]
- Minimum Energy Fixed-Priority Scheduling for Variable Voltage ProcessorGang Quan, Xiaobo Hu. 782-787 [doi]
- A Dynamic Voltage Scaling Algorithm for Dynamic-Priority Hard Real-Time Systems Using Slack Time AnalysisWoonseok Kim, Jihong Kim, Sang Lyul Min. 788-794 [doi]
- Extending Synchronous Languages for Generating Abstract Real-Time ModelsGeorge Logothetis, Klaus Schneider. 795-803 [doi]
- An Interconnect-Aware Methodology for Analog and Mixed Signal Design, Based on High Bandwidth (Over 40 Ghz) On-Chip Transmission Line Approach David Goren, Michael Zelikson, Tiberiu C. Galambos, Rachel Gordin, Betty Livshitz, Alon Amir, Anatoly Sherman, Israel A. Wagner. 804-811 [doi]
- Closed-Form Crosstalk Noise Metrics for Physical Design ApplicationsLauren Hui Chen, Malgorzata Marek-Sadowska. 812-819 [doi]
- Formulation of Low-Order Dominant Poles for Y-Matrix of InterconnectsQinwei Xu, Pinaki Mazumder. 820-825 [doi]
- Library Compatible Ceff for Gate-Level TimingBernard N. Sheehan. 826-831 [doi]
- Self-Checking Scheme for the On-Line Testing of Power Supply NoiseCecilia Metra, Luca Schiano, Bruno Riccò, Michele Favalli. 832-836 [doi]
- Automatic Modifications of High Level VHDL Descriptions for Fault Detection or ToleranceRégis Leveugle. 837-841 [doi]
- Exploiting Idle Cycles for Algorithm Level Re-ComputingKaijie Wu, Ramesh Karri. 842-846 [doi]
- New Techniques for Speeding-Up Fault-Injection CampaignsLuis Berrojo, Isabel González, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Luis Entrena, Celia López. 847-853 [doi]
- System Design for FlexibilityChristian Haubelt, Jürgen Teich, Kai Richter, Rolf Ernst. 854-861 [doi]
- Accurate Area and Delay Estimators for FPGAsAnshuman Nayak, Malay Haldar, Alok N. Choudhary, Prithviraj Banerjee. 862-869 [doi]
- A Powerful System Design Methodology Combining OCAPI and Handel-C for Concept EngineeringKlaus Buchenrieder, Andreas Pyttel, Alexander Sedlmeier. 870-874 [doi]
- Automated Concurrency Re-Assignment in High Level System Models for Efficient System-Level SimulationNick Savoiu, Sandeep K. Shukla, Rajesh K. Gupta. 875-883 [doi]
- From System Specification To Layout: Seamless Top-Down Design Methods for Analog and Mixed-Signal ApplicationsR. Sommer, Irmtraud Rugen-Herzig, E. Hennig, Umberto Gatti, Piero Malcovati, Franco Maloberti, Karsten Einwich, Christoph Clauß, Peter Schwarz, G. Noessing. 884-893 [doi]
- Memory System Connectivity ExplorationPeter Grun, Nikil D. Dutt, Alexandru Nicolau. 894-901 [doi]
- Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled MemorySambuddhi Hettiaratchi, Peter Y. K. Cheung, Thomas J. W. Clarke. 902-908 [doi]
- Multiple-Precision Circuits Allocation Independent of Data-Objects LengthMaría C. Molina, José M. Mendías, Román Hermida. 909-915 [doi]
- Efficient Model Reduction of Linear Time-Varying Systems via Compressed Transient System FunctionEmad Gad, Michel S. Nakhla. 916-922 [doi]
- Passive Constrained Rational Approximation Algorithm Using Nevanlinna-Pick InterpolationCarlos P. Coelho, Luis Miguel Silveira, Joel R. Phillips. 923-930 [doi]
- Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov MethodsYiran Chen, Venkataramanan Balakrishnan, Cheng-Kok Koh, Kaushik Roy. 931-937 [doi]
- An Optimal Algorithm for the Automatic Generation of March TestsAlfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto. 938-943 [doi]
- Minimal Test for Coupling Faults in Word-Oriented MemoriesA. J. van de Goor, Magdy S. Abadir, Alan Carlin. 944-948 [doi]
- Maximizing Impossibilities for Untestable Fault IdentificationMichael S. Hsiao. 949-953 [doi]
- Automated Modeling of Custom Digital Circuits for TestSoumitra Bose. 954-963 [doi]
- False Path Elimination in Quasi-Static SchedulingG. Arrigoni, L. Duchini, Claudio Passerone, Luciano Lavagno, Yosinori Watanabe. 964-970 [doi]
- A Data Analysis Method for Software Performance PredictionGianluca Bontempi, Wido Kruijtzer. 971-976 [doi]
- A Code Transformation-Based Methodology for Improving I-Cache Performance of DSP ApplicationsNikolaos D. Liveris, Nikolaos D. Zervas, Dimitrios Soudris, Constantinos E. Goutis. 977-983 [doi]
- A Compiler-Based Approach for Improving Intra-Iteration Data ReuseMahmut T. Kandemir. 984-991 [doi]
- European CAD from the 60 s to the New MilleniumJoseph Borel. 992-993 [doi]
- Design Technology for Networked Reconfigurable FPGA PlatformsSteve Guccione, Diederik Verkest, Ivo Bolsens. 994-999 [doi]
- High-Speed Non-Linear Asynchronous PipelinesRecep O. Ozdag, Peter A. Beerel, Montek Singh, Steven M. Nowick. 1000-1007 [doi]
- Single-Track Asynchronous Pipeline Templates Using 1-of-N EncodingMarcos Ferretti, Peter A. Beerel. 1008-1015 [doi]
- Power-Manageable Scheduling Technique for Control Dominated High-Level SynthesisChunhong Chen, Majid Sarrafzadeh. 1016-1020 [doi]
- Practical Instruction Set Design and Compiler Retargetability Using Static Resource ModelsQin Zhao, Bart Mesman, Twan Basten. 1021-1027 [doi]
- Hierarchical Simulation of Substrate Coupling in Mixed-Signal ICs Considering the Power Supply NetworkThomas Brandtner, Robert Weigel. 1028-1032 [doi]
- Fast Method to Include Parasitic Coupling in Circuit SimulationsB. L. A. Van Thielen, G. A. E. Vandenbosch. 1033-1037 [doi]
- Accurate Estimating Simultaneous Switching Noises by Using Application Specific Device ModelingLi Ding 0002, Pinaki Mazumder. 1038-1043 [doi]
- Macromodeling of Digital I/O Ports for System EMC Assessment Igor S. Stievano, Flavio G. Canavero, Ivan A. Maio, Z. Chen, Wiren D. Becker, George A. Katopis. 1044-1049 [doi]
- Formal Verification Techniques: Industrial Status and PerspectivesJoel Blasquez, Marten van Hulst, Andrea Fedeli, Jean-Luc Lambert, Dominique Borrione, Coby Hanoch, Pierre Bricaud. 1050-1051 [doi]
- Low Power Embedded Software Optimization Using Symbolic AlgebraArmita Peymandoust, Tajana Simunic, Giovanni De Micheli. 1052-1058 [doi]
- An Adaptive Dictionary Encoding Scheme for SOC Data BusesTiehan Lv, Wayne Wolf, Jörg Henkel, Haris Lekatsas. 1059 [doi]
- Power Efficient Embedded Processor Ip s through Application-Specific Tag Compression in Data CachesPeter Petrov, Alex Orailoglu. 1065-1071 [doi]
- Systematic Power-Performance Trade-Off in MPEG-4 by Means of Selective Function Inlining Steered by Address Optimization OpportunitiesMartin Palkovic, Miguel Miranda, Francky Catthoor. 1072-1079 [doi]
- An Approach to Model Checking for Nonlinear Analog Systems1080 [doi]
- Speeding up SAT for EDASlawomir Pilarski, Gracia Hu. 1081 [doi]
- Search-Based SAT Using Zero-Suppressed BDDsFadi A. Aloul, Maher N. Mneimneh, Karem A. Sakallah. 1082 [doi]
- An Encoding Technique for Low Power CMOS Implementations of ControllersManuel Martínez, Maria J. Avedillo, José M. Quintana, H. Süß, Manfred Koegst. 1083 [doi]
- Composition Trees in Finding Best Variable Orderings for ROBDDsElena Dubrova. 1084 [doi]
- A Direct Mapping System for Datapath Module and FSM Implementation into LUT-Based FPGAs Joerg Abke, Erich Barke. 1085 [doi]
- Concurrent and Selective Logic Extraction with Timing ConsiderationPeyman Rezvani, Massoud Pedram. 1086 [doi]
- Improved Technology Mapping for PAL-Based Devices Using a New Approach to Multi-Output Boolean FunctionsDariusz Kania. 1087 [doi]
- Efficient and Effective Redundancy Removal for Million-Gate CircuitsMichel R. C. M. Berkelaar, Koen Van Eijk. 1088 [doi]
- Visualization of Partial Order Models in VLSI Design FlowAlexandre V. Bystrov, Maciej Koutny, Alexandre Yakovlev. 1089 [doi]
- High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication SystemsJean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Jerome Quartana. 1090 [doi]
- Power-Efficient Trace CachesJie S. Hu, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. 1091 [doi]
- Reducing Cache Access Energy in Array-Intensive ApplicationMahmut T. Kandemir, Ibrahim Kolcu. 1092 [doi]
- The Use of Runtime Configuration Capabilities for Networked Embedded SystemsCarsten Nitsch, Udo Kebschull. 1093 [doi]
- A SAT Solver Using Software and Reconfigurable HardwareIouliia Skliarova, António de Brito Ferrari. 1094 [doi]
- A New Time Model for the Specification, Design, Validation and Synthesis of Embedded Real-Time SystemsRalf Münzenberger, Matthias Dörfel, Frank Slomka, Richard Hofmann. 1095 [doi]
- Improved Constraints for Multiprocessor System SchedulingMartin Grajcar, Werner Grass. 1096 [doi]
- Maximizing Conditonal Reuse by Pre-Synthesis TransformationsOlga Peñalba, José M. Mendías, Román Hermida. 1097 [doi]
- Control Circuit Templates for Asynchronous Bundled-Data PipelinesSunan Tugsinavisut, Peter A. Beerel. 1098 [doi]
- Transforming Arbitrary Structures into Topologically Equivalent Slicing StructuresOlivier Peyran, Wenjun Zhuang. 1099 [doi]
- A New Formulation for SOC Floorplan Area Minimization ProblemChih-Hung Lee, Yu-Chung Lin, Wen-Yu Fu, Chung-Chiao Chang, Tsai-Ming Hsieh. 1100 [doi]
- Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan DesignChris C. N. Chu, Evangeline F. Y. Young. 1101 [doi]
- EZ Encoding: A Class of Irredundant Low Power Codes for Data Address and Multiplexed Address BusesYazdan Aghaghiri, Massoud Pedram, Farzan Fallah. 1102 [doi]
- Estimation of Power Consumption in Encoded Data BusesAlberto García Ortiz, Lukusa D. Kabulepa, Manfred Glesner. 1103 [doi]
- Optimization Techniques for Design of General and Feedback Linear Analog Amplifier with Symbolic AnalysisTran chi Hieu. 1104 [doi]
- Critical Comparison among Some Analog Fault Diagnosis Procedures Based on Symbolic TechniquesAntonio Luchetta, Stefano Manetti, Maria Cristina Piccirilli. 1105 [doi]
- The Selective Pull-Up (SP) Noise Immunity Scheme for Dynamic CircuitsMircea R. Stan, Avishek Panigrahi. 1106 [doi]
- Substrate Parasitic Extraction for RF Integrated CircuitsAndreia Cathelin, D. Saias, Didier Belot, Y. Leclercq, F. Clément. 1107 [doi]
- A Complete Phase-Locked Loop Power Consumption ModelDavid Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin. 1108 [doi]
- Statistical Timing Driven Partitioning for VLSI CircuitsCristinel Ababei, Kia Bazargan. 1109 [doi]
- DAISY-CT: A High-Level Simulation Tool for Continuous-Time Delta Sigma ModulatorsKenneth Francken, Martin Vogels, Ewout Martens, Georges G. E. Gielen. 1110 [doi]
- Automated Optimal Design of Switched-Capacitor FiltersA. Hassibi, Maria del Mar Hershenson. 1111 [doi]
- On-Chip Inductance Models: 3D or Not 3D?Tao Lin, Michael W. Beattie, Lawrence T. Pileggi. 1112 [doi]
- Simple and Efficient Approach for Shunt Admittance Parameters Calculations of VLSI On-Chip Interconnects on Semiconducting SubstrateHasan Ymeri, Bart Nauwelaers, Karen Maex, David De Roest, Michele Stucchi, Servaas Vandenberghe. 1113 [doi]
- Compact Macromodel for Lossy Coupled Transmission LinesRoni Khazaka, Michel S. Nakhla. 1114 [doi]
- An EMC-Compliant Design Method of High-Density Integrated CircuitsJean-Luc Levant, Mohammed Ramdani. 1115 [doi]
- Finding a Common Fault Response for Diagnosis during Silicon DebugIrith Pomeranz, Janusz Rajski, Sudhakar M. Reddy. 1116 [doi]
- I::DDT:: Testing of Embedded CMOS SRAMsSuriya Ashok Kumar, Rafic Z. Makki, David W. Binkley. 1117 [doi]
- Fault Detection and Diagnosis Using Wavelet Based Transient Current AnalysisSwarup Bhunia, Kaushik Roy. 1118 [doi]
- An Efficient Test and Diagnosis Scheme for the Feedback Type of Analog Circuits with Minimal Added CircuitsJun-Weir Lin, Chung-Len Lee, Jwu E. Chen. 1119 [doi]
- On the Use of an Oscillation-Based Test Methodology for CMOS Micro-Electro-Mechanical SystemsVincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet. 1120 [doi]
- Directed-Binary Search in Logic BIST DiagnosticsRohit Kapur, Thomas W. Williams, M. Ray Mercer. 1121 [doi]
- An Evolutionary Approach to the Design of On-Chip Pseudorandom Test Pattern GeneratorsMichele Favalli, Marcello Dalpasso. 1122 [doi]
- Fault Isolation Using Tests for Non-Isolated BlocksIrith Pomeranz, Yervant Zorian. 1123 [doi]
- A Heuristic for Test Scheduling at System LevelMarie-Lise Flottes, Julien Pouget, Bruno Rouzeyre. 1124 [doi]
- Formulation of SOC Test Scheduling as a Network Transportation ProblemSandeep Koranne, Vishal Suhas Choudhary. 1125 [doi]
- A Novel Methodology for the Concurrent Test of Partial and Dynamically Reconfigurable SRAM-Based FPGAsManuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira. 1126 [doi]
- Efficient On-Line Testing Method for a Floating-Point Iterative Array DividerAlexander V. Drozd, M. V. Lobachev, J. V. Drozd. 1127 [doi]
- An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW CoresAndrea Bona, Mariagiovanna Sami, Donatella Sciuto, Vittorio Zaccaria, Cristina Silvano, Roberto Zafalon. 1128 [doi]
- The Fraunhofer Knowledge Network (FKN) for Training in Critical Design DisciplinesAnton Sauer, Günter Elst, Ludger Krahn, Werner John. 1129 [doi]
- Comparative Analysis and Application of Data Repository Infrastructure for Collaboration-Enabled Distributed Design EnvironmentsLeandro Soares Indrusiak, Manfred Glesner, Ricardo Augusto da Luz Reis. 1130 [doi]
- FlexBench: Reuse of Verification IP to Increase ProductivityBernd Stöhr, Michael Simmons, Joachim Geishauser. 1131 [doi]
- Mappability Estimation of Architecture and AlgorithmJuha-Pekka Soininen, Jari Kreku, Yang Qu. 1132 [doi]
- Behavioural Modelling of Operational Amplifier Faults Using VHDL-AMSPeter R. Wilson, J. Neil Ross, Mark Zwolinski, Andrew D. Brown, Yavuz Kiliç. 1133 [doi]
- A Parallel LCC Simulation SystemKlaus Hering. 1134 [doi]
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- Towards a Kernel Language for Heterogeneous ComputingDag Björklund, Johan Lilius. 1136 [doi]
- Top-Down System Level Design Methodology Using SpecC, VCC and SystemCLukai Cai, Daniel Gajski, Paul Kritzinger, Mike Olivarez. 1137 [doi]
- Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded ProcessorsLaura Pozzi, Miljan Vuletic, Paolo Ienne. 1138 [doi]
- Steady State Calculation of Oscillators Using Continuation MethodsHans Georg Brachtendorf, S. Lampe, Rainer Laur, Robert C. Melville, Peter Feldmann. 1139 [doi]