Soumitra Bose - researchr alias

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Viewing Publication 1 - 23 from 23

2007

Estimating stuck fault coverage in sequential logic using state traversal and entropy analysisSoumitra Bose, Vishwani D. Agrawal. itc 2007: 1-10 [doi]

Delay fault simulation with bounded gate delay modeSoumitra Bose, Hillary Grimes, Vishwani D. Agrawal. itc 2007: 1-10 [doi]

Delay Test Quality Evaluation Using Bounded Gate DelaysSoumitra Bose, Vishwani D. Agrawal. vts 2007: 23-28 [doi]

2006

Upper Bounding Fault Coverage by Structural Analysis and Signal MonitoringVishwani D. Agrawal, Soumitra Bose, Vijay Gangaram. vts 2006: 88-93 [doi]

Fault Coverage Estimation for Non-Random Functional Input SequencesSoumitra Bose, Vishwani D. Agrawal. itc 2006: 1-10 [doi]

2005

Schematic array models for associative and non-associative memory circuitsSoumitra Bose, Amit Nandi. tcad, 24(10):1582-1593, 2005. [doi]

2004

Modeling Custom Digital Circuits for TestSoumitra Bose. et, 20(6):591-609, 2004. [doi]

Extraction of Schematic Array Models for Memory CircuitsSoumitra Bose, Amit Nandi. date 2004: 570-577 [doi]

2002

Automated Modeling of Custom Digital Circuits for TestSoumitra Bose. date 2002: 954-963 [doi]

1998

Deriving Logic Systems for Path Delay Test GenerationSoumitra Bose, Prathima Agrawal, Vishwani D. Agrawal. TC, 47(8):829-846, 1998.

1997

Algorithms for Switch Level Delay Fault SimulationSoumitra Bose, Vishwani D. Agrawal, Thomas G. Szymanski. itc 1997: 982-991

1995

Sequential logic path delay test generation by symbolic analysisSoumitra Bose, Vishwani D. Agrawal. ats 1995: 353 [doi]

1993

1992

Concurrent Fault Simulation of Logic Gates and Memory Blocks on Message Passing MulticomputersSoumitra Bose, Prathima Agrawal. dac 1992: 332-335 [doi]

PARTHENON: A Parallel Theorem Prover for Non-Horn ClausesSoumitra Bose, Edmund M. Clarke, David E. Long, Spiro Michaylov. JAR, 8(2):153-181, 1992.

1989

PARTHENON: A Parallel Theorem Prover for Non-Horn ClausesSoumitra Bose, Edmund M. Clarke, David E. Long, Spiro Michaylov. lics 1989: 80-89

Verifying pipelined hardware using symbolic logic simulationSoumitra Bose, Allan L. Fisher. iccd 1989: 217-221 [doi]

1988

PARTHENON: A Parallel Theorem Prover for Non-Horn ClausesP. E. Allen, Soumitra Bose, Edmund M. Clarke, Spiro Michaylov. cade 1988: 764-765

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