Table of Contents

• Test Structure and Testing of the Microsoft XBOX 360/sup TM/ Processor High Speed Front Side BusTung Pham, Brian Koehler, Daniel Young, Louis Bushard. 1-6 [doi]
• DRAM-Specific Space of Memory TestsZaid Al-Ars, Said Hamdioui, A. J. van de Goor, Georgi Gaydadjiev, Jörg E. Vollrath. 1-10 [doi]
• Optimizing the Cost of Test at Intel Using per Device DataRobert Edmondson, Gregory Iovino, Richard Kacprowicz. 1-8 [doi]
• Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based DesignsSantiago Remersaro, Xijiang Lin, Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski. 1-10 [doi]
• A Robust, Self-Tuning CMOS Circuit for Built-in Go/No-Go Testing of Synthesizer Phase NoiseErdem Serkan Erdogan, Sule Ozev. 1-10 [doi]
• Testing MRAM for Write Disturbance FaultChin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Chien-Chung Hung, Young-Shying Chen, Ming-Jer Kao. 1-9 [doi]
• A High Speed Reduced Pin Count JTAG InterfaceLee Whetsel. 1-10 [doi]
• Fully-Digital Time-To-Digital Converter for ATE with Autonomous CalibrationJochen Rivoir. 1-10 [doi]
• Test Data Compression of 100x for Scan-Based BISTMasayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Tatsuru Matsuo, Takahisa Hiraide, Hideaki Konishi, Michiaki Emori, Takashi Aikyo. 1-10 [doi]
• The Design and Validation of IP for DFM/DFY AssuranceRobert C. Aitken. 1-7 [doi]
• Exact At-speed Delay Fault Grading in Sequential CircuitsMahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi. 1-10 [doi]
• At-Speed Structural Test For High-Performance ASICsVikram Iyengar, Toshihiko Yokota, Kazuhiro Yamada, Theo Anemikos, Bob Bassett, Mike Degregorio, Rudy Farmer, Gary Grise, Mark Johnson, Dave Milton, Mark Taylor, Frank Woytowich. 1-10 [doi]
• Issues on Test Optimization with Known Good Dies and Known Defective Dies - A Statistical PerspectiveBenjamin N. Lee, Li-C. Wang, Magdy S. Abadir. 1-10 [doi]
• On-chip Test and Repair of Memories for Static and Dynamic FaultsSanjay K. Thakur, Rubin A. Parekhji, Arun N. Chandorkar. 1-10 [doi]
• A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCsTsu-Wei Tseng, Jin-Fu Li, Chih-Chiang Hsu, Alex Pao, Kevin Chiu, Eliot Chen. 1-9 [doi]
• Fault Detection by Output Response Comparison of Identical Circuits Using Half-Frequency Compatible SequencesIrith Pomeranz, Sudhakar M. Reddy. 1-10 [doi]
• High-Voltage and High-Power PLL Diagnostics using Advanced Cooling and Emission ImagesFranco Stellari, Peilin Song, Tim Diemoz, Alan J. Weger, Tami Vogel, Steve Wilson, John Pennings, Richard F. Rizzolo. 1-10 [doi]
• Perfect data reconstruction algorithm of time interleaved ADCsFang Xu. 1-6 [doi]
• A Real-Time Delta-Time-to-Voltage Converter for Clock Jitter MeasurementKiyotaka Ichiyama, Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma. 1-8 [doi]
• DIBPro: Automatic Diagnostic Program Generation ToolVenkat Kalyanaraman, Bruce C. Kim, Pramodchandran N. Variyam, Sasikumar Cherubal. 1-8 [doi]
• BIST Power Reduction Using Scan-Chain Disable in the Cell ProcessorChristian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Mäding, Jens Leenstra. 1-8 [doi]
• Novel Architecture for On-Chip AC Characterization of I/OsN. Vijayaraghavan, Balwant Singh, Saurabh Singh, Vishal Srivastava. 1-10 [doi]
• IEEE P1581 - Getting More Board Test Out of Boundary ScanHeiko Ehrenberg. 1-10 [doi]
• Characteristic States and Cooperative Game Based Search for Efficient Sequential ATPG and Design ValidationXiaoding Chen, Michael S. Hsiao. 1-10 [doi]
• Evaluating and Improving Transient Error Tolerance of CMOS Digital VLSI CircuitsChong Zhao, Sujit Dey. 1-10 [doi]
• Integrated RF-CMOS Transceivers challenge RF TestFrank Demmerle. 1-8 [doi]
• Self-Checking and Self-Diagnosing 32-bit Microprocessor MultiplierMahmut Yilmaz, Derek Hower, Sule Ozev, Daniel J. Sorin. 1-10 [doi]
• Automatic generation of instruction sequences targeting hard-to-detect structural faults in a processorSankar Gurumurthy, Shobha Vasudevan, Jacob A. Abraham. 1-9 [doi]
• Characterize Predicted vs Actual IR Drop in a Chip Using Scan ClocksZahi S. Abuhamdeh, Philip Pears, Jeff Remmers, Alfred L. Crouch, Bob Hannagan. 1-8 [doi]
• Embedded Memory Diagnosis: An Industrial WorkflowDavide Appello, Vincenzo Tancorre, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda. 1-9 [doi]
• Combinational Logic Soft Error CorrectionSubhasish Mitra, Ming Zhang, Saad Waqas, Norbert Seifert, Balkaran S. Gill, Kee Sup Kim. 1-9 [doi]
• Massively Parallel Validation of High-Speed Serial Interfaces using Compact Instrument ModulesMohamed Hafed, Daniel Watkins, Clarence Tam, Bardia Pishdad. 1-10 [doi]
• An Enhanced EDAC Methodology for Low Power PSRAMPo-Yuan Chen, Yi-Ting Yeh, Chao-Hsun Chen, Jen-Chieh Yeh, Cheng-Wen Wu, Jeng-Shen Lee, Yu-Chang Lin. 1-10 [doi]
• The Economics of Implementing Scan Compression to Reduce Test Data Volume and Test Application TimeChris Allsup. 1-9 [doi]
• X-Press Compactor for 1000x Reduction of Test DataJanusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab. 1-10 [doi]
• On-line Boundary-Scan Testing in Service of Extended ProductsIlka Reis, Peter Collins, Marc van Houcke. 1-10 [doi]
• Efficient Latch and Clock Structures for System-on-Chip Test FlexibilityDavid E. Lackey. 1-7 [doi]
• SiP-TAP: JTAG for SiPFrans de Jong, Alex S. Biewenga. 1-10 [doi]
• Test Compression for FPGAsMehdi Baradaran Tahoori, Subhasish Mitra. 1-9 [doi]
• A Rapid Yield Learning Flow Based on Production Integrated Layout-Aware DiagnosisMartin Keim, Nagesh Tamarapalli, Huaxing Tang, Manish Sharma, Janusz Rajski, Chris Schuermyer, Brady Benware. 1-10 [doi]
• Built-in Fault Diagnosis for Tunable Analog Systems Using an Ensemble MethodHongjoong Shin, Joonsung Park, Jacob A. Abraham. 1-10 [doi]
• The Role of ATPG Fault Diagnostics in Driving Physical AnalysisRoger Nicholson, Cathy Kardach, Bruce Cory. 1-7 [doi]
• Embedded Memory Field Returns - Trials and TribulationsJitendra Khare, Amit B. Shah, Ashok Raman, Girish Rayas. 1-6 [doi]
• Testing of Precision DACs Using Low-Resolution ADCs with DitheringLe Jin, Hosam Haggag, Randall L. Geiger, Degang Chen. 1-10 [doi]
• A Novel and Practical Control Scheme for Inter-Clock At-Speed TestingHiroshi Furukawa, Xiaoqing Wen, Laung-Terng Wang, Boryau Sheu, Zhigang Jiang, Shianling Wu. 1-10 [doi]
• The Challenge of Testing the ARM CORTEX-A8/sup TM/ Microprocessor CoreTeresa L. McLaurin. 1-10 [doi]
• IEEE P1687: Toward Standardized Access of Embedded InstrumentationKen Posse, Al Crouch, Jeff Rearick, Bill Eklow, Mike Laisne, Ben Bennetts, Jason Doege, Mike Ricchetti, J.-F. Cote. 1-8 [doi]
• Selective and Accurate Fail Data Capture in Compression Environment for Volume DiagnosticsAjay Khoche, Domenico Chindamo, Michael Braun, Martin Fischer. 1-10 [doi]
• Technique to Detect RF Interface and Contact Issues During Production TestingMartin Dresler. 1-6 [doi]
• Alternate Test of RF Front Ends with IP Constraints: Frequency Domain Test Generation and ValidationSelim Sermet Akbay, Jose L. Torres, Julie M. Rumer, Abhijit Chatterjee, Joel Amtsfield. 1-10 [doi]
• Linearity Test of Analog-to-Digital Converters Using Kalman FilteringLe Jin, Degang Chen, Randall L. Geiger. 1-9 [doi]
• Pattern Pruner: Automatic Pattern Size Reduction Method that Uses Computational Intelligence-Based TestingEric Liau Chee Hong, Manfred Menke, Thomas Janik, Doris Schmitt-Landsiedel. 1-10 [doi]
• The Design, Implementation and Analysis of Test ExperimentsPeter Maxwell. 1-9 [doi]
• Defect-Oriented and Time-Constrained Wafer-Level Test-Length Selection for Core-Based Digital SoCsSudarshan Bahukudumbi, Krishnendu Chakrabarty. 1-10 [doi]
• A Survey of Test Problems and SolutionsJeff Rearick. 1-10 [doi]
• Using Limited Dependence Sequential Expansion for Decompressing Test VectorsAvijit Dutta, Nur A. Touba. 1-9 [doi]
• Test Economics - What can a Board/System Test Engineer do to Influence Supply Operation MetricsSylvain Tourangeau, Bill Eklow. 1-9 [doi]
• OCI: Open Compression InterfaceBruce Cory, Rohit Kapur, Mick Tegethoff, Mark Kassab, Brion L. Keller, Kee Sup Kim, Dwayne Burek, Steven F. Oakland, Benoit Nadeau-Dostie. 1-4 [doi]
• Diagnostic Test Generation for Arbitrary FaultsNaresh K. Bhatti, Ronald D. Blanton. 1-9 [doi]
• Estimating Error Rate during Self-Test via One's CountingShideh Shahidi, Sandeep K. Gupta. 1-9 [doi]
• Lead Free Through Hole Technology (THT) and Contact Repeatability in In-Circuit TestRosa D. Reinosa. 1-10 [doi]
• A Unified Approach to Test Generation and Test Data Volume ReductionYung-Chieh Lin, Kwang-Ting Cheng. 1-10 [doi]
• Classifying Bad Chips and Ordering Test SetsFrançois-Fabien Ferhani, Edward J. McCluskey. 1-10 [doi]
• Reusable, Low-cost, and Flexible Multidrop System JTAG ArchitectureHung-chi Lihn. 1-10 [doi]
• Structural Testing of High-Speed Serial Buses: A Case Study AnalysisEric Johnson. 1-9 [doi]
• Fault Coverage Estimation for Non-Random Functional Input SequencesSoumitra Bose, Vishwani D. Agrawal. 1-10 [doi]
• ISI Injection Filter Designs Using PIN and Varactor Diodes for SerDes Testing on ATEFengming Zhang, Warren Necoechea. 1-7 [doi]
• A Predictable Robust Fully Programmable Analog Gaussian Noise Source for Mixed-Signal/Digital ATESadok Aouini, Gordon W. Roberts. 1-10 [doi]
• A Functional Coverage Metric for Estimating the Gate-Level Fault Coverage of Functional TestsSungchul Park, Li Chen, Praveen Parvathala, Srinivas Patil, Irith Pomeranz. 1-10 [doi]
• An Efficient Pruning Method to Guide the Search of Precision Tests in Statistical Timing SpaceLeonard Lee, Li-C. Wang. 1-10 [doi]
• Periodic Jitter Amplitude Calibration with Walking StrobeLucy Liu, Eddie Lew. 1-8 [doi]
• A Novel Ganged DAC Solution for Multi-Site TestingJoseph Kwan, Qing Zhao. 1-6 [doi]
• Power Supply Noise in Delay TestingJing Wang 0006, D. M. H. Walker, Ananta K. Majhi, Bram Kruseman, Guido Gronthoud, Luis Elvira Villagra, Paul van de Wiel, Stefan Eichenberger. 1-10 [doi]
• The Power of Exhaustive Bridge Diagnosis using IDDQ Speed, Confidence, and ResolutionDoug Heaberlin. 1-10 [doi]
• HDL Program Slicing to Reduce Bounded Model Checking Search OverheadJen-Chieh Ou, Daniel G. Saab, Jacob A. Abraham. 1-7 [doi]
• Cycle-Accurate Test Power Modeling and its Application to SoC Test SchedulingSoheil Samii, Erik Larsson, Krishnendu Chakrabarty, Zebo Peng. 1-10 [doi]
• A Study of Implication Based Pseudo Functional TestingManan Syal, Kameshwar Chandrasekar, Vishnu C. Vimjam, Michael S. Hsiao, Yi-Shing Chang, Sreejit Chakravarty. 1-10 [doi]
• A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain DesignsShih-Ping Lin, Chung-Len Lee, Jwu E. Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu. 1-8 [doi]
• Diagnosis with Limited Failure InformationYu Huang 0005, Wu-Tung Cheng, Nagesh Tamarapalli, Janusz Rajski, Randy Klingenberg, Will Hsu, Yuan-Shih Chen. 1-10 [doi]
• Bit Error Rate Estimation for Improving Jitter Testing of High-Speed Serial LinksDongwoo Hong, Kwang-Ting Cheng. 1-10 [doi]
• Testing of UltraSPARC T1 Microprocessor and its ChallengesP. J. Tan, Tung Le, Keng-Hian Ng, Prasad Mantri, James Westfall. 1-10 [doi]
• Signature Analyzer Design for Yield Learning SupportNishant Patil, Subhasish Mitra, Steven S. Lumetta. 1-10 [doi]
• Data Analysis Techniques for CMOS Technology Characterization and Product Impact AssessmentAnne Gattiker, Manjul Bhushan, Mark B. Ketchen. 1-10 [doi]
• Timing Defect Diagnosis in Presence of Crosstalk for Nanometer TechnologyVishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski. 1-10 [doi]
• Interconnect Delay Fault Test on Boards and SoCs with Multiple Clock DomainsHyunbean Yi, Jaehoon Song, Sungju Park. 1-7 [doi]
• A Framework of High-quality Transition Fault ATPG for Scan CircuitsSeiji Kajihara, Shohei Morishima, Akane Takuma, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato. 1-6 [doi]
• Signature Based Diagnosis for Logic BISTWu-Tung Cheng, Manish Sharma, Thomas Rinderknecht, Liyang Lai, Chris Hill. 1-9 [doi]
• Cache Resident Functional Microprocessor Testing: Avoiding High Speed IO IssuesIsmet Bayraktaroglu, Jim Hunt, Daniel Watkins. 1-7 [doi]
• Structural Tests for Jitter Tolerance in SerDes ReceiversStephen K. Sunter, Aubin Roy. 1-10 [doi]
• Improved Match-Line Test and Repair Methodology Including Power-Supply Noise Testing for Content-Addressable MemoriesRahul Nadkarni, Igor Arsovski, Reid Wistort, Valerie Chickanosky. 1-9 [doi]
• A Study of Per-Pin Timing Jitter ScopeTakahiro J. Yamaguchi, Satoshi Iwamoto, Masahiro Ishida, Mani Soma. 1-7 [doi]
• Multi Strobe Circuit for 2.133GHz Memory Test SystemKazuhiro Yamamoto, Masakatsu Suda, Toshiyuki Okayasu, Hirokatsu Niijima, Koichi Tanaka. 1-9 [doi]
• Comparison of Delay Tests on SiliconWangqi Qiu, D. M. H. Walker, Neil Simpson, Divya Reddy, Anthony Moore. 1-10 [doi]
• A Logic Diagnosis Methodology for Improved Localization and Extraction of Accurate Defect BehaviorRao Desineni, Osei Poku, Ronald D. Blanton. 1-10 [doi]
• Testable Design for Adaptive Linear Equalizer in High-Speed Serial LinksMitchell Lin, Kwang-Ting Cheng. 1-10 [doi]
• Improving Precision Using Mixed-level Fault DiagnosisEnamul Amyeen, Debashis Nayak, Srikanth Venkataraman. 1-10 [doi]
• Analog Boundary-Scan Description Language (ABSDL) for Mixed-Signal Board TestBambang Suparjo, Adam W. Ley, Adam Cron, Heiko Ehrenberg. 1-9 [doi]
• Fault Modeling and Detection for Drowsy SRAM CachesWei Pei, Wen-Ben Jone, Yiming Hu. 1-10 [doi]
• Very-Low Voltage (VLV) and VLV Ratio (VLVR) Testing for Quality, Reliability, and Outlier DetectionJeffrey L. Roehr. 1-6 [doi]
• Recognition of Sensitized Longest Paths in Transition Delay TestShuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Yasuyuki Noduyama, Yasuo Sato. 1-6 [doi]
• Dependable Network-on-Chip Router Able to Simultaneously Tolerate Soft Errors and CrosstalkArthur Pereira Frantz, Fernanda Lima Kastensmidt, Luigi Carro, Érika F. Cota. 1-9 [doi]
• Jump Simulation: A Technique for Fast and Precise Scan Chain Fault DiagnosisYu-Long Kao, Wei-Shun Chuang, James Chien-Mo Li. 1-9 [doi]
• Improving Transition Fault Test Pattern Quality through At-Speed DiagnosisNandu Tendolkar, Dawit Belete, Bill Schwarz, Bob Podnar, Akshay Gupta, Steve Karako, Wu-Tung Cheng, Alex Babin, Kun-Han Tsai, Nagesh Tamarapalli, Greg Aldrich. 1-9 [doi]
• Prospects for Wafer-Level Testing of Gigascale Chips with Electrical and Optical I/O InterconnectsHiren D. Thacker, James D. Meindl. 1-7 [doi]
• Implementation of Solder-bead Probing in High Volume ManufacturingMadhavan Doraiswamy, James J. Grealish. 1-10 [doi]
• Multi-Gigahertz Testing of Wafer-Level Packaged DevicesA. M. Majid, David C. Keezer, Jayasanker Jayabalan, Mihai Rotaru. 1-10 [doi]
• Debug of the CELL Processor: Moving the Lab into SiliconMack W. Riley, Nathan Chelstrom, Mike Genden, Shoji Sawamura. 1-9 [doi]
• Behavioral Test EconomicsScott Davidson, Anthony P. Ambler, Helen Davidson. 1-9 [doi]
• Seamless Integration of SER in Rewiring-Based Design Space ExplorationSobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, Andreas G. Veneris. 1-9 [doi]
• Design for Board and System Level Structural Test and DiagnosisToai Vo, Zhiyuan Wang, Ted Eaton, Pradipta Ghosh, Huai Li, Young Lee, Weili Wang, Hong Shin Jun, Rong Fang, Dan Singletary, Xinli Gu. 1-10 [doi]
• Cost Effective Outliers Screening with Moving Limits and Correlation Testing for Analogue ICsLiquan Fang, Mohammed Lemnawar, Yizi Xing. 1-10 [doi]
• An Accelerated Jitter Tolerance Test Technique on Ate for 1.5GB/S and 3GB/S Serial-ATAYongquan Fan, Yi Cai, Liming Fang, Anant Verma, William Burchanowski, Zeljko Zilic, Sandeep Kumar. 1-10 [doi]
• What is DFM & DFY and Why Should I Care ?Rajesh Raina. 1-9 [doi]
• Fully automated semiconductor operating condition testingThomas Nirmaier, Wolfgang Spirkl, Eric Liau Chee Hong. 1-9 [doi]
• Test Software Generation Productivity and Code Quality Improvement by applying Software Engineering TechniquesStefan Vock, Markus Schmid, Hans Martin von Staudt. 1-8 [doi]
• A Case Study of Using IEEE P1687 (IJTAG) for High-Speed Serial I/O Characterization and TestingJeff Rearick, Aaron Volz. 1-8 [doi]
• Modeling and Testing Process Variation in Nanometer CMOSMehrdad Nourani, Arun Radhakrishnan. 1-10 [doi]
• Combining Internal Probing with Artificial Neural Networks for Optimal RFIC TestingSofiane Ellouz, Patrice Gamand, Christophe Kelma, Bertrand Vandewiele, Bruno Allard. 1-9 [doi]