Igor Arsovski - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 13 from 13

2018

2 TCAM Using Two-Phase-Pre-Charge ML Sensing and Power-Grid Pre-Conditioning to Reduce Ldi/dt Power-Supply Noise by 50%Igor Arsovski, Akhilesh Patil, Robert M. Houle, Michael Fragano, Ramon Rodriguez, Raymond Kim, Van Butler. jssc, 53(1):155-163, 2018. [doi]

2017

2 TCAM using two-phase-precharge ML sensing and power-grid preconditioning to reduce Ldi/dt power-supply noise by 50%Igor Arsovski, Michael Fragano, Robert M. Houle, Akhilesh Patil, Van Butler, Raymond Kim, Ramon Rodriguez, Tom Maffitt, Joseph J. Oler, John Goss, Christopher Parkinson, Michael A. Ziegerhofer, Steven Burns. isscc 2017: 212-213 [doi]

2013

Tail-Bit Tracking circuit with degraded VGS bit-cell mimic array for a 50% search-time and 200mV Vmin improvement in a Ternary Content Addressable MemoryIgor Arsovski, Travis Hebig, John Goss, Paul Grzymkowski, Josh Patch. cicc 2013: 1-4 [doi]

A 32 nm 0.58-fJ/Bit/Search 1-GHz Ternary Content Addressable Memory Compiler Using Silicon-Aware Early-Predict Late-Correct Sensing With Embedded Deep-Trench Capacitor Noise MitigationIgor Arsovski, Travis Hebig, Daniel Dobson, Reid Wistort. jssc, 48(4):932-939, 2013. [doi]

A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reductionHarold Pilo, Chad A. Adams, Igor Arsovski, Robert M. Houle, Steve Lamphier, Michael M. Lee, Frank Pavlik, Sushma N. Sambatur, Adnan Seferagic, Richard Wu, Mohammad I. Younus. isscc 2013: 322-323 [doi]

2012

1Gsearch/sec Ternary Content Addressable Memory compiler with silicon-aware Early-Predict Late-Correct single-ended sensingIgor Arsovski, Travis Hebig, Daniel Dobson, Reid Wistort. vlsic 2012: 116-117 [doi]

A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability EnhancementsHarold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John Gabric, Robert M. Houle, Steve Lamphier, Carl Radens, Adnan Seferagic. jssc, 47(1):97-106, 2012. [doi]

2011

A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancementsHarold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John Gabric, Robert M. Houle, Steve Lamphier, Frank Pavlik, Adnan Seferagic, Liang-Yu Chen, Shang-Bin Ko, Carl Radens. isscc 2011: 254-256 [doi]

2006

Self-referenced sense amplifier for across-chip-variation immune sensing in high-performance Content-Addressable MemoriesIgor Arsovski, Reid Wistort. cicc 2006: 453-456 [doi]

Improved Match-Line Test and Repair Methodology Including Power-Supply Noise Testing for Content-Addressable MemoriesRahul Nadkarni, Igor Arsovski, Reid Wistort, Valerie Chickanosky. itc 2006: 1-9 [doi]

2005

Low-noise embedded CAM with reduced slew-rate match-lines and asynchronous search-linesIgor Arsovski, Rahul Nadkarni. cicc 2005: 447-450 [doi]

2003

A mismatch-dependent power allocation technique for match-line sensing in content-addressable memoriesIgor Arsovski, Ali Sheikholeslami. jssc, 38(11):1958-1966, 2003. [doi]

A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing schemeIgor Arsovski, Trevis Chandler, Ali Sheikholeslami. jssc, 38(1):155-158, 2003. [doi]

Sign in or sign up to see more results.

runs on WebDSL