John Gabric - researchr alias

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Viewing Publication 1 - 4 from 4

2012

A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability EnhancementsHarold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John Gabric, Robert M. Houle, Steve Lamphier, Carl Radens, Adnan Seferagic. jssc, 47(1):97-106, 2012. [doi]

2011

A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancementsHarold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John Gabric, Robert M. Houle, Steve Lamphier, Frank Pavlik, Adnan Seferagic, Liang-Yu Chen, Shang-Bin Ko, Carl Radens. isscc 2011: 254-256 [doi]

2009

An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power ManagementVinod Ramadurai, Harold Pilo, John Andersen, Geordie Braceras, John Gabric, Daniel Geise, Steve Lamphier, Yue Tan. jssc, 44(1):155-162, 2009. [doi]

2008

A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power ManagementHarold Pilo, Vaidyanathan Ramadurai, Geordie Braceras, John Gabric, Steve Lamphier, Yue Tan. isscc 2008: 378-379 [doi]

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