Table of Contents

• Green Electronics: Environmental Impacts, Power, E-WasteJan Sevenhans, Rudolf Koch. 12-13 [doi]
• MEMS for Frequency Synthesis and Wireless RF Communications (or Life without Quartz Crystal)Christian Enz, Ernesto Perea, Ken Cioffi. 14-15 [doi]
• The 2nd Wave of the Digital Consumer Revolution: Challenges and Opportunities!Hyung Kyu Lim. 18-23 [doi]
• Surface and Tangible Computing, and the "Small" Matter of People and DesignBill Buxton. 24-29 [doi]
• Embedded Processing at the Heart of Life and StyleMike Muller. 32-37 [doi]
• Why Can't A Computer Be More Like A Brain? Or What To Do With All Those Transistors?Jeff Hawkins. 38-41 [doi]
• A 128×128 Single-Photon Imager with on-Chip Column-Level 10b Time-to-Digital Converter Array Capable of 97ps ResolutionCristiano Niclass, Claudio Favi, Theo Kluter, Marek Gersbach, Edoardo Charbon. 44-45 [doi]
• A 5000S/s Single-Chip Smart Eye-Tracking SensorDongsoo Kim, Jihyun Cho, Seunghyun Lim, Dongmyung Lee, Gunhee Han. 46-47 [doi]
• A 3MPixel Multi-Aperture Image Sensor with 0.7μm Pixels in 0.11μm CMOSKeith Fife, Abbas El Gamal, H.-S. Philip Wong. 48-49 [doi]
• A 140dB-Dynamic-Range MOS Image Sensor with In-Pixel Multiple-Exposure SynthesisTakayoshi Yamada, Shigetaka Kasuga, Takahiko Murata, Yoshihisa Kato. 50-51 [doi]
• A White-RGB CFA-Patterned CMOS Image Sensor with Wide Dynamic RangeYoshitaka Egawa, Nagataka Tanaka, Nobuhiro Kawai, Hiromichi Seki, Akira Nakao, Hiroto Honda, Y. Lida, Makoto Monoi. 52-53 [doi]
• A 3.6pW/frame·pixel 1.35V PWM CMOS Imager with Dynamic Pixel Readout and no Static Bias CurrentK. Kagawau, Sanshiro Shishido, Masahiro Nunoshita, Jun Ohta. 54-55 [doi]
• A CMOS Image Sensor Integrating Column-Parallel Cyclic ADCs with On-Chip Digital Error Correction CircuitsShoji Kawahito, Jong Ho Park, Keigo Isobe, Suhaidi Shafie, T. Lida, Takashi Mizota. 56-57 [doi]
• A 2Mpixel 1/4-inch CMOS Image Sensor with Enhanced Pixel Architecture for Camera Phones and PC CamerasJ. Moholt, T. Willassen, John Ladd, Xiaofeng Fan, D. Gans. 58-59 [doi]
• Low-Crosstalk and Low-Dark-Current CMOS Image-Sensor Technology Using a Hole-Based DetectorEric Stevens, Hirofumi Komori, Hung Doan, Hiroaki Fujita, Jeffery Kyan, Christopher Parks, Gang Shi, Cristian Tivarus, Jian Wu. 60-61 [doi]
• A CMOS Image Sensor with a Buried-Channel Source FollowerXinyang Wang, Martijn F. Snoeij, Padmakumar R. Rao, Adri Mierop, Albert J. P. Theuwissen. 62-63 [doi]
• A Widely-Tunable Reconfigurable CMOS Analog Baseband IC for Software-Defined RadioMasaki Kitsunezuka, Shinichi Hori, Tadashi Maeda. 66-67 [doi]
• A Gain-Boosted Discrete-Time Charge-Domain FIR LPF with Double-Complementary MOS Parametric AmplifiersA. Yoshizawa, S. Lida. 68-69 [doi]
• A Continuous-Time Hexagonal Field-Programmable Analog Array in 0.13μm CMOS with 186MHz GBWJoachim Becker, Fabian Henrici, Stanis Trendelenburg, Maurits Ortmanns, Yiannos Manoli. 70-71 [doi]
• th-Order 100μA 280MHz Source-Follower-Based Single-loop Continuous-Time FilterStefano D'Amico, Marcello De Matteis, Andrea Baschirotto. 72-73 [doi]
• A Current-Feedback Instrumentation Amplifier with 5μV Offset for Bidirectional High-Side Current-SensingJ. Frerik Witte, Johan H. Huijsing, Kofi A. A. Makinwa. 74-75 [doi]
• A BiCMOS Operational Amplifier Achieving 0.33μV°C Offset Drift using Room-Temperature TrimmingMuhammed Bolatkale, Michiel A. P. Pertijs, Wilko J. Kindt, Johan H. Huijsing, Kofi A. A. Makinwa. 76-77 [doi]
• 130dB-DR Transimpedance Amplifier with Monotonic Logarithmic Compression and High-Current MonitorDaniel Micusik, Horst Zimmermann. 78-79 [doi]
• A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC® ProcessorMarc Tremblay, Shailender Chaudhry. 82-83 [doi]
• Implementation of a Third-Generation 16-Core 32-Thread Chip-Multithreading SPARCs® ProcessorGeorgios Konstadinidis, Mamun Rashid, Peter F. Lai, Yukio Otaguro, Yannis Orginos, Sudhendra Parampalli, Mark Steigerwald, Shriram Gundala, Rambabu Pyapali, Leonard Rarick, Ilyas Elkin, Yuefei Ge, Ishwar Parulkar. 84-85 [doi]
• Migration of Cell Broadband Engine from 65nm SOI to 45nm SOIOsamu Takahashi, C. Adams, D. Ault, Erwin Behnen, O. Chiang, Scott R. Cottier, Paula K. Coulman, James Culp, Gilles Gervais, M. S. Gray, Y. Itaka, C. J. Johnson, F. Kono, L. Maurice, Kevin W. McCullen, Lam Nguyen, Y. Nishino, Hiromi Noro, Jürgen Pille, Mack W. Riley, M. Shen, Chiaki Takano, Shunsaku Tokito, Tina Wagner, Hiroshi Yoshihara. 86-87 [doi]
• TILE64 - Processor: A 64-Core SoC with Mesh InterconnectShane Bell, Bruce Edwards, John Amann, Rich Conlin, Kevin Joyce, Vince Leung, John MacKay, Mike Reif, Liewei Bao, John F. Brown III, Matthew Mattina, Chyi-Chang Miao, Carl Ramey, David Wentzlaff, Walker Anderson, Ethan Berger, Nat Fairbanks, Durlov Khan, Froilan Montenegro, Jay Stickney, John Zook. 88-89 [doi]
• An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing CompilerMasayuki Ito, Toshihiro Hattori, Yutaka Yoshida, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Yoshihiko Yasu, Atsushi Hasegawa, Masashi Takada, Hiroyuki Mizuno, Kunio Uchiyama, Toshihiko Odaka, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara. 90-91 [doi]
• A 65nm 2-Billion-Transistor Quad-Core Itanium® ProcessorBlaine A. Stackhouse, Brian S. Cherkauer, Michael K. Gowan, Paul E. Gronowski, Chris Lyles. 92-93 [doi]
• Circuit Design for Voltage Scaling and SER Immunity on a Quad-Core Itanium® ProcessorDan Krueger, Erin Francom, Jack Langsdorf. 94-95 [doi]
• An 8Gb/s Transceiver with 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss BackplaneKoji Fukuda, Hiroki Yamashita, Fumio Yuki, Masayoshi Yagyu, Ryo Nemoto, Takashi Takemoto, Tatsuya Saito, Norio Chujo, Keiichi Yamamoto, Hisaaki Kanai, Atsuhiro Hayashi. 98-99 [doi]
• A 40Gb/s CMOS Serial-Link Receiver with Adaptive Equalization and CDRChih-Fan Liao, Shen-Iuan Liu. 100-101 [doi]
• A 20Gb/s Duobinary Transceiver in 90nm CMOSJri Lee, Ming-Shuan Chen, Huaide Wang. 102-103 [doi]
• A 6Gb/s RX Equalizer Adapted Using Direct Measurement of the Equalizer Output AmplitudeH. Uchiki, Y. Ota, M. Tani, Yasushi Hayakawa, Katsushi Asahina. 104-105 [doi]
• A 10Gb/s IEEE 802.3an-Compliant Ethernet Transceiver for 100m UTP Cable in 0.13μm CMOSSandeep Gupta, José Tellado-Mourelo, Sridhar Begur, Frank Yang, Vishnu Balan, Michael Inerfield, Dariush Dabiri, John Dring, Sachin Goel, Kumaraguru Muthukumaraswamy, Frank McCarthy, Glenn Golden, Jiangfeng Wu, Susan Arno, Sanjay Kasturia. 106-107 [doi]
• A Serial Data Transmitter for Multiple 10Gb/s Communication Standards in 0.13μm CMOSAndrew C. Y. Lin, Marc J. Loinaz. 108-109 [doi]
• A T-Coil-Enhanced 8.5Gb/s High-Swing source-Series-Terminated Transmitter in 65nm Bulk CMOSMarcel A. Kossel, Christian Menolfi, Jonas Weiss, Peter Buchmann, George von Büren, Lucio Rodoni, Thomas Morf, Thomas Toifl, Martin L. Schmatz. 110-111 [doi]
• A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital CalibrationHyung-Joon Chi, Jae-Seung Lee, Seong-Hwan Jeon, Seung-Jun Bae, Jae-Yoon Sim, Hong June Park. 112-113 [doi]
• A 1.8Gpulses/s UWB Transmitter in 90nm CMOSMurat Demirkan, Richard R. Spencer. 116-117 [doi]
• A 0.18μm CMOS 802.15.4a UWB Transceiver for Communication and LocalizationYuanjin Zheng, M. Annamalai Arasu, King-Wan Wong, Yen Ju The, A. P. H. Suan, Duy Duong Tran, Wooi Gan Yeoh, Dim-Lee Kwong. 118-119 [doi]
• A CMOS UWB Camera with 7×7 Simultaneous Active PixelsTa-Shun Chu, Hossein Hashemi. 120-121 [doi]
• A Fully Integrated 14-Band 3.1-to-10.6GHz 0.13μm SiGe BiCMOS UWB RF TransceiverOliver Werther, Mark Cavin, Angelika Schneider, Robert Renninger, Bo Liang, Long Bu, Yalin Jin, John Marcincavage. 122-123 [doi]
• UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection LockingStefano Dal Toso, Andrea Bevilacqua, Marc Tiebout, Stefano Marsili, Christoph Sandner, Andrea Gerosa, Andrea Neviani. 124-125 [doi]
• A 3-to-10GHz 14-Band CMOS Frequency Synthesizer with Spurs Reduction for MB-OFDM UWB SystemTai-You Lu, Wei-Zen Chen. 126-127 [doi]
• A 0.6-to-10GHz Receiver Front-End in 45nm CMOSRemco van de Beek, Jos Bergervoet, Harish Kundur, Domine Leenaerts, Gerard Van der Weide. 128-129 [doi]
• A 90nm CMOS 60GHz RadioStephane Pinel, Saikat Sarkar, Padmanava Sen, Bevin G. Perumana, David Yeh, Debasis Dawn, Joy Laskar. 130-131 [doi]
• A 60kb/s-to-10Mb/s 0.37nJ/b Adaptive-Frequency-Hopping Transceiver for Body-Area NetworkNamjun Cho, Jeabin Lee, Long Yan, Joonsung Bae, Sunyoung Kim, Hoi-Jun Yoo. 132-133 [doi]
• Life Thermoscope: Integrated Microelectronics for Visualizing Hidden Life RhythmKazuo Yano, Nobuo Sato, Yoshihiro Wakisaka, Satomi Tsuji, Norio Ohkubo, Miki Hayakawa, Norihiko Moriwaki. 136-137 [doi]
• A 1V, Micropower System-on-Chip for Vital-Sign Monitoring in Wireless Body Sensor NetworksAlan Chi Wai Wong, Declan McDonagh, Ganesh Kathiresan, Okundu C. Omeni, Omar El-Jamaly, Thomas C.-K. Chan, Paul Paddan, Alison Burdett. 138-139 [doi]
• CMOS Mini Nuclear Magnetic Resonance System and its Application for Biomolecular SensingYong Liu, Nan Sun, Hakho Lee, Ralph Weissleder, Donhee Ham. 140-141 [doi]
• CMOS Imager Technologies for Biomedical ApplicationsJoachim N. Burghartz, Thorsten Engelhardt, Heinz-Gerd Graf, Christine Harendt, Harald Richter, Cor Scherjon, Karsten Warkentin. 142-143 [doi]
• A 1600-pixel Subretinal Chip with DC-free Terminals and ±2V Supply Optimized for Long Lifetime and High Stimulation EfficiencyAlbrecht Rothermel, Volker Wieczorek, Liu Liu, Alfred Stett, Matthias Gerhardt, Alex Harscher, Steffen Kibbel. 144-145 [doi]
• A 128-Channel 6mW Wireless Neural Recording IC with On-the-Fly Spike Sorting and UWB TansmitterMoo Sung Chae, Wentai Liu, Zhi Yang, Tung-Chien Chen, Jungsuk Kim, Mohanasankar Sivaprakasam, Mehmet R. Yuce. 146-147 [doi]
• A 256x256 CMOS Microelectrode Array for Extracellular Neural Stimulation of Acute Brain SlicesNa Lei, Brendon O. Watson, Jason N. MacLean, Rafael Yuste, Kenneth L. Shepard. 148-149 [doi]
• A 1.12mW Continuous Healthcare Monitor Chip Integrated on a Planar Fashionable Circuit BoardHyejung Kim, Yongsang Kim, Young-Se Kwon, Hoi-Jun Yoo. 150-151 [doi]
• From Silicon Aether and BackSatoshi Tanaka, Marc Tiebout, Ali Hajimiri. 152-153 [doi]
• Unusual Data-Converter TechniquesVenu Gopinathan, Boris Murmann. 154-155 [doi]
• Private Equity: Fight them or Invite themSreedhar Natarajan, Nicky Lu. 156-157 [doi]
• Trusting our Lives to SensorsJohannes Solhusvik, Tim Denison. 158-159 [doi]
• An 8μW Heterodyning Chopper Amplifier for Direct Extraction of 2μVrms Neuronal BiomarkersTimothy Denison, Wesley Santa, Randy Jensen, Dave Carlson, Gregory Molnar, Al Avestruz. 162-163 [doi]
• A 200μW Eight-Channel Acquisition ASIC for Ambulatory EEG SystemsRefet Firat Yazicioglu, Patrick Merken, Robert Puers, Chris Van Hoof. 164-165 [doi]
• A Microsystem for Time-Resolved Fluorescence Analysis using CMOS Single-Photon Avalanche Diodes and Micro-LEDsBruce Rae, Chris Griffin, Keith R. Muir, John M. Girkin, Erdan Gu, David R. Renshaw, Edoardo Charbon, Martin D. Dawson, Robert K. Henderson. 166-167 [doi]
• CMOS Electro-Chemical DNA-Detection Array with On-Chip ADCFlavio Heer, Manuel Keller, George Yu, Jiri Janata, Mira Josowicz, Andreas Hierlemann. 168-169 [doi]
• A Fingerprint Sensor with Impedance Sensing for Fraud DetectionToshishige Shimamura, Hiroki Morimura, Nobuhiro Shimoyama, Tomomi Sakata, Satoshi Shigematsu, Katsuyuki Machida, Mamoru Nakanishi. 170-171 [doi]
• A 10b 75ns CMOS Scanning-Display-Driver System for QVGA LCDsIliana Fujimori-Chen, Rikky Muller, W. Kan, M. Fazio, A. Farrell, David H. Whitney. 172-173 [doi]
• A Direct-Type Fast Feedback Current Driver for Medium-to Large-Size AMOLED DisplaysJinyong Jeon, Yong-Joon Jeon, Young-Suk Son, Kwang-Chan Lee, Hyung-Min Lee, Seungchul Jung, Kang-Ho Lee, Gyu-Hyeong Cho. 174-175 [doi]
• A Compact Low-Power CDAC Architecture for Mobile TFT-LCD Driver ICsYoon Kyung Choi, Zhong-Yuan Wu, KyungMyun Kim, Yong-Hun Lee, Min-Soo Cho, Hyo-Sun Kim, Dong-Hun Lee, Won-Gab Jung. 176-177 [doi]
• A 95GHz Receiver with Fundamental-Frequency VCO and Static Frequency Divider in 65nm Digital CMOSEkaterina Laskin, Mehdi Khanpour, Ricardo Andres Aroca, K. K. W. Tang, Patrice Garcia, Sorin P. Voinigescu. 180-181 [doi]
• A Robust 24mW 60GHz Receiver in 90nm Standard CMOSBagher Afshar, Yanjie Wang, Ali M. Niknejad. 182-183 [doi]
• A 52GHz Phased-Array Receiver Front-End in 90nm Digital CMOSKaren Scheir, Stephane Bronckers, Jonathan Borremans, Piet Wambacq, Yves Rolain. 184-185 [doi]
• A Scalable 6-to-18GHz Concurrent Dual-Band Quad-Beam Phased-Array Receiver in CMOSSanggeun Jeon, Yu-Jiu Wang, Hua Wang, Florian Bohn, Arun Natarajan, Aydin Babakhani, Ali Hajimiri. 186-187 [doi]
• A Near-Field Modulation Technique Using Antenna Reflector SwitchingAydin Babakhani, David B. Rutledge, Ali Hajimiri. 188-189 [doi]
• A 60GHz CMOS Receiver Using a 30GHz LOAli Parsa, Behzad Razavi. 190-191 [doi]
• A 22.3dB Voltage Gain 6.1dB NF 60GHz LNA in 65nm CMOS with Differential OutputChristopher Weyers, Pierre Mayr, Johannes W. Kunze, Ulrich Langmann. 192-193 [doi]
• A 2kV ESD-Protected 18GHz LNA with 4dB NF in 0.13μm CMOSYiqun Cao, Vadim Issakov, Marc Tiebout. 194-195 [doi]
• A Broadband Distributed Amplifier with Internal Feedback Providing 660GHz GBW in 90nm CMOSAmin Arbabian, Ali M. Niknejad. 196-197 [doi]
• A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGEHsiang-Hui Chang, Ping-Ying Wang, Jing-Hong Conan Zhan, Bing-Yu Hsieh. 200-201 [doi]
• Single-Chip Tri-Band WCDMA/HSDPA Transceiver without External SAW Filters and with Integrated TX Power ControlBernard Tenbroek, Jon Strange, Dimitris Nalbantis, Christopher Jones, Paul Fowers, Steve Brett, Christophe Beghein, Federico Beffa. 202-203 [doi]
• Equalization of IM3 Products in Wideband Direct-Conversion ReceiversEdward A. Keehr, Ali Hajimiri. 204-205 [doi]
• A Fully Integrated Quad-Band GPRS/EDGE Radio in 0.13μm CMOSHooman Darabi, Alireza Zolfaghari, Henrik Jensen, John C. Leete, Behnam Mohammadi, Janice Chiu, Qiang Li, Zhimin Zhou, Paul Lettieri, Yuyu Chang, Amir Hadji-Abdolhamid, Paul Chang, Mohammad Nariman, Iqbal Bhatti, Ali Medi, L. Serrano, Jared Welz, Kambiz Shoarinejad, S. M. Shajedul Hasan, Jesse Castaneda, Jay Kim, Huey Tran, P. Kilcoyne, R. Chen, Bobby Lee, B. Zhao, Brima Ibrahim, Maryam Rofougaran, Ahmadreza Rofougaran. 206-207 [doi]
• 2 Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOSRobert B. Staszewski, Dirk Leipold, Oren Eliezer, Mitch Entezari, Khurram Muhammad, Imran Bashir, Chih-Ming Hung, John L. Wallberg, Roman Staszewski, Patrick Cruise, Sameh Rezeq, Sudheer Vemulapalli, Khurram Waheed, Nathen Barton, Meng-Chang Lee, C. Fernando, Kenneth Maggio, Tom Jung, Imtinan Elahi, S. Larson, Thomas Murphy, Gennady Feygin, Irene Yuanying Deng, Terry Mayhugh Jr., Y. C. Ho, K.-M. Low, C. Lin, J. Jaehnig, J. Kerr, Jaimin Mehta, S. Glock, T. Almholt, S. Bhatara. 208-209 [doi]
• Integration of a SiP for GSM/EDGE in CMOS TechnologyGuiseppe Li Puma, Ernst Fristan, Paolio De Nicola, Cyril Vannier, Braam Greyling, Sylvatore Piccolella. 210-211 [doi]
• A Low-Power WCDMA Transmitter with an Integrated Notch FilterAhmad Mirzaei, Hooman Darabi. 212-213 [doi]
• A 1.2V 0.2-to-6.3GHz Transceiver with Less Than -29.5dB EVM@-3dBm and a Choke/Coil-Less Pre-Power AmplifierShouhei Kousai, Daisuke Miyashita, Junji Wadatsumi, Asuka Maki, Takahiro Sekiguchi, Rui Ito, Mototsugu Hamada. 214-215 [doi]
• A 24GHz Sub-Harmonic Receiver Front-End with Integrated Multi-Phase LO Generation in 65nm CMOSAndrea Mazzanti, Marco Sosio, Matteo Repossi, Francesco Svelto. 216-217 [doi]
• A 2.7V 9.8Gb/s Burst-Mode TIA with Fast Automatic Gain Locking and Coarse Threshold ExtractionTine De Ridder, Peter Ossieur, B. Baekelandt, Cedric Mélange, Johan Bauwelinck, Colin Ford, Xing-Zhi Qiu, Jan Vandewege. 220-221 [doi]
• A 10Gb/s Laser-Diode Driver with Active Back-Termination in 0.18μm CMOSChia-Ming Tsai, Mao-Cheng Chiu. 222-223 [doi]
• A 20/10/5/2.5Gb/s Power-scaling Burst-Mode CDR Circuit Using GVCO/Div2/DFF Tri-mode CellsChe-Fu Liang, Shen-Iuan Liu. 224-225 [doi]
• A 10.3125Gb/s Burst-Mode CDR Circuit using a δσ DACJun Terada, Kazuyoshi Nishimura, Shunji Kimura, Hiroaki Katsurai, Naoto Yoshimoto, Yusuke Ohtomo. 226-227 [doi]
• A 40Gb/s CDR with Adaptive Decision-Point Control Using Eye-Opening-Monitor FeedbackHidemi Noguchi, Nobuhide Yoshida, Hiroaki Uchida, Manabu Ozaki, Shunichi Kanemitsu, Shigeki Wada. 228-229 [doi]
• A 96Gb/s-Throughput Transceiver for Short-Distance Parallel Optical LinksSushmit Goswami, Tino Copani, Anuj Jain, Habib Karaki, Bert Vermeire, Hugh J. Barnaby, Gregory J. Fetzer, Rick Vercillo, Sayfe Kiaei. 230-231 [doi]
• A 90nm CMOS DSP MLSD Transceiver with Integrated AFE for Electronic Dispersion Compensation of Multi-mode Optical Fibers at 10Gb/sOscar E. Agazzi, Diego E. Crivelli, Mario Rafael Hueda, Hugo S. Carrer, German C. Luna, Ali Nazemi, Carl Grace, Bilal Kobeissy, Cindra Abidin, Mohammad Kazemi, Mahyar Kargar, César Marquez, Sumant Ramprasad, Federico Bollo, Vladimir A. Posse, Stephen Wang, Georgios Asmanis, George Eaton, Norman Swenson, Tom Lindsay, Paul Voois. 232-233 [doi]
• A 10Gb/s MLSE-based Electronic-Dispersion-Compensation IC with Fast Power-Transient Management for WDM Add/Drop NetworksHyeon-Min Bae, Andrew C. Singer, Jonathan B. Ashbrook, Naresh R. Shanbhag. 234-235 [doi]
• An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOSVito Giannini, Pierluigi Nuzzo, Vincenzo Chironi, Andrea Baschirotto, Geert Van der Plas, Jan Craninckx. 238-239 [doi]
• Highly Interleaved 5b 250MS/s ADC with Redundant Channels in 65nm CMOSBrian P. Ginsburg, Anantha P. Chandrakasan. 240-241 [doi]
• A 150MS/s 133μW 7b ADC in 90nm digital CMOS Using a Comparator-Based Asynchronous Binary-Search sub-ADCGeert Van der Plas, Bob Verbruggen. 242-243 [doi]
• A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADCMichiel van Elzakker, Ed van Tuijl, Paul F. J. Geraedts, Daniël Schinkel, Eric A. M. Klumperink, Bram Nauta. 244-245 [doi]
• A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with Time-Domain ComparatorAndrea Agnes, Edoardo Bonizzoni, Piero Malcovati, Franco Maloberti. 246-247 [doi]
• A 14b 100MS/s Pipelined ADC with a Merged Active S/H and First MDACByung Geun Lee, Byung-Moo Min, Gabriele Manganaro, Jonathan W. Valvano. 248-249 [doi]
• A 1.2V 4.5mW 10b 100MS/s Pipeline ADC in a 65nm CMOSMounir Boulemnakher, Eric Andre, Jocelyn Roux, Frederic Paillardet. 250-251 [doi]
• A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOSBob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas. 252-253 [doi]
• A Sub-1W to 2W Low-Power IA Processor for Mobile Internet Devices and Ultra-Mobile PCs in 45nm Hi-Κ Metal Gate CMOSGianfranco Gerosa, Steve Curtis, Michael D'Addeo, Bo Jiang, Belliappa Kuttanna, Feroze Merchant, Binta Patel, Mohammed H. Taufique, Haytham Samarchi. 256-257 [doi]
• A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power TechniquesGordon Gammie, Alice Wang, Minh Chau, Sumanth Gururajarao, Robert Pitts, Fabien Jumel, Stacey Engel, Philippe Royannez, Rolf Lagerquist, Hugh Mair, Jeff Vaccani, Greg Baldwin, Keerthi Heragu, Rituparna Mandal, Michael Clinton, Don Arden, Uming Ko. 258-259 [doi]
• A 65nm Single-Chip Application and Dual-Mode Baseband Processor with Partial Clock Activation and IP-MMUM. Naruse, Tatsuya Kamei, Toshihiro Hattori, Takahiro Irita, Kenichi Nitta, Takao Koike, Shinichi Yoshioka, Koji Ohno, M. Saigusa, M. Sakata, Y. Kodama, Y. Arai, T. Komuro. 260-261 [doi]
• A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS TechnologyShuou Nomura, Fumihiko Tachibana, Tetsuya Fujita, Chen Kong Teh, Hiroyuki Usui, Fumiyuki Yamane, Yukimasa Miyamoto, Chaiyasit Kumtornkittikul, Hiroyuki Hara, Takahiro Yamashita, Jun Tanabe, Masaru Uchiyama, Y. Tsuboi, Takashi Miyamori, Takeshi Kitahara, Hironori Sato, Y. Homma, S. Matsumoto, K. Seki, Y. Watanabe, Mototsugu Hamada, Makoto Takahashi. 262-263 [doi]
• 2 HSDPA Turbo Decoder ASIC in 0.13μm CMOSChristian Benkeser, Andreas Burg, Teo Cupaiuolo, Qiuting Huang. 264-265 [doi]
• 2 70mW Fully-Programmable Baseband Processor for Mobile WiMAX and DVB-T/H in 0.12μm CMOSAnders Nilsson, Eric Tell, Dake Liu. 266-267 [doi]
• A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOSSergey Romanovsky, A. Katoch, Arun Achyuthan, C. O'Connell, Sreedhar Natarajan, C. Huang, Chuan-Yu Wu, Min-Jer Wang, C.-J. Wang, P. Chen, R. Hsieh. 270-271 [doi]
• A 170GB/s 16Mb Embedded DRAM with Data-Bus Charge-RecyclingKim Hardee, M. Parris, O. F. Jones, D. Butler, M. Mound, G. W. Jones, T. Egging, T. Arakawa, K. Sasahara, K. Taniguchi, M. Miyabayashi. 272-273 [doi]
• 2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic ProcessDinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Y. Borkar, Vivek De, Ali Keshavarzi. 274-275 [doi]
• An 833MHz Pseudo-Two-Port Embedded DRAM for Graphics ApplicationsMariko Kaku, Hitoshi Iwai, Takeshi Nagai, Masaharu Wada, Atsushi Suzuki, Tomohisa Takai, Naoko Itoga, Takayuki Miyazaki, Takayuki Iwai, Hiroyuki Takenaka, Takehiko Hojo, Shinji Miyano, Nobuaki Otsuka. 276-277 [doi]
• A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction TechniquesSeung-Jun Bae, Young-Soo Sohn, Kwang-Il Park, Kyoung-Ho Kim, Dae-Hyun Chung, Jingook Kim, Si-Hong Kim, Min-Sang Park, Jae-Hyung Lee, Sam-Young Bang, Ho-Kyung Lee, In-Soo Park, Jae-Sung Kim, Dae-Hyun Kim, Hye-Ran Kim, Yong-Jae Shin, Cheol-Goo Park, Gil-Shin Moon, Ki-Woong Yeom, Kang-Young Kim, Jae Young Lee, Hyang-Ja Yang, Seong-Jin Jang, Joo-Sun Choi, Young-Hyun Jun, Kinam Kim. 278-279 [doi]
• Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM InterfaceDong Uk Lee, Shin-Deok Kang, Nak-Kyu Park, Hyun-Woo Lee, Young-Kyoung Choi, Jung Woo Lee, Seung-Wook Kwack, Hyeong Ouk Lee, Won-Joo Yun, Sang-Hoon Shin, Kwan-Weon Kim, Young-Jung Choi, Ye Seok Yang. 280-281 [doi]
• A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS TechnologyWon-Joo Yun, Hyun-Woo Lee, Dongsuk Shin, Shin-Deok Kang, Ji-Yeon Yang, Hyeng-Ouk Lee, Dong Uk Lee, Sujeong Sim, Young-Ju Kim, Won Jun Choi, Keun-Soo Song, Sang-Hoon Shin, Hyang-Hwa Choi, Hyung-Wook Moon, Seung-Wook Kwack, Jung Woo Lee, Young-Kyoung Choi, Nak-Kyu Park, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Ye Seok Yang. 282-283 [doi]
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• A 107pJ/b 100kb/s 0.18μm Capacitive-Coupling Transceiver for Printable Communication SheetLechang Liu, Makoto Takamiya, Tsuyoshi Sekitani, Yoshiaki Noguchi, Shintaro Nakano, Koichiro Zaitsu, Tadahiro Kuroda, Takao Someya, Takayasu Sakurai. 292-293 [doi]
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• An 11Gb/s Inductive-Coupling Link with Burst TransmissionNoriyuki Miura, Yoshinori Kohama, Yasufumi Sugimori, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda. 298-299 [doi]
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• A Full-Wave Rectifier for Interfacing with Multi-Phase Piezoelectric Energy HarvestersNathaniel J. Guilar, Rajeevan Amirtharajah, Paul J. Hurst. 302-303 [doi]
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• A 360mW 105Mb/s DVB-S2 Compliant Codec based on 64800b LDPC and BCH Codes enabling Satellite-Transmission Portable DevicesPascal Urard, L. Paumier, V. Heinrich, N. Raina, Nitin Chawla. 310-311 [doi]
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• A 65nm Sub-Vt Microcontroller with Integrated SRAM and Switched-Capacitor DC-DC ConverterJoyce Kwong, Yogesh K. Ramadass, Naveen Verma, Markus Koesler, Korbinian Huber, Hans Moormann, Anantha Chandrakasan. 318-319 [doi]
• A Discrete-Time Mixing Receiver Architecture with Wideband Harmonic RejectionZhiyu Ru, Eric A. M. Klumperink, Bram Nauta. 322-323 [doi]
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• A Low-Noise, Wide-BW 3.6GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise CancellationChun-Ming Hsu, Matthew Z. Straayer, Michael H. Perrott. 340-341 [doi]
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• A 90μW 12MHz Relaxation Oscillator with a -162dB FOMPaul F. J. Geraedts, Ed van Tuijl, Eric A. M. Klumperink, Gerard Wienk, Bram Nauta. 348-349 [doi]
• A 0.5-to-480MHz Self-Referenced CMOS Clock Generator with 90ppm Total Frequency Error and Spread-Spectrum CapabilityMichael S. McCorquodale, Scott M. Pernia, Justin D. O'Day, Gordon A. Carichner, Eric D. Marsman, Nam Nguyen, Sundus Kubba, Si Nguyen, Jonathan J. Kuhn, Richard B. Brown. 350-351 [doi]
• A Temperature-Compensated Digitally-Controlled Crystal Pierce Oscillator for Wireless ApplicationsShayan Farahvash, Chee Quek, Monica Mak. 352-353 [doi]
• A 1×2 MIMO Multi-Band CMOS Transceiver with an Integrated Front-End in 90nm CMOS for 802.11a/g/n WLAN ApplicationsOfir Degani, Mark Ruberto, Emanuel Cohen, Yishai Eilat, Benjamin Jann, Fabian Cossoy, Nikolay Telzhensky, Tzvi Maimon, Gregory Normatov, Rotem Banin, Ori Ashkenazi, Assaf Ben Bassat, Sharon Zaguri, Gabriel Hara, Mario Zajac, Eyal Shaviv, Shay Wail, Amir Fridman, Richard Lin, Shai Gross. 356-357 [doi]
• A Dual-Band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LANLalitkumar Nathawad, Masoud Zargari, Hirad Samavati, Srenik Mehta, Alireza Kheirkhahi, Phoebe Chen, Ke Gong, Babak Vakili-Amini, Justin A. Hwang, Mike Shuo-Wei Chen, Manolis Terrovitis, Brian Kaczynski, Sotirios Limotyrakis, Michael P. Mack, Haitao Gan, MeeLan Lee, Shahram Abdollahi-Alibeik, Burcin Baytekin, Keith Onodera, Sunetra Mendis, Andrew Chang, S. Jen, David Su, Bruce A. Wooley. 358-359 [doi]
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• A Single-Chip CMOS Radio SoC for v2.1 Bluetooth ApplicationsDavid Weber, William W. Si, Shahram Abdollahi-Alibeik, MeeLan Lee, Richard Chang, Hakan Dogan, Susan Luschas, Paul Husted. 364-365 [doi]
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• 2 2.4GHz Front-End Receiver in 90nm CMOS for IEEE 802.15.4 WPANManuel Camus, Benoit Butaye, Luc Garcia, Mathilde Sié, Bruno Pellat, Thierry Parra. 368-369 [doi]
• 2 Quadrature Front-End RX for ZigBee and WPAN ApplicationsAntonio Liscidini, Marika Tedeschi, Rinaldo Castello. 370-371 [doi]
• A DDFS Driven Mixing-DAC with Image and Harmonic Rejection CapabilitiesAdrian Maxim, Ramin Khoini-Poorfard, Mitchell Reid, James T. Kao, Charles D. Thompson, Richard A. Johnson. 372-373 [doi]
• A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-Κ Metal-Gate CMOS TechnologyFatih Hamzaoglu, Kevin Zhang, Yin Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Yong-Gee Ng, Andrei Pavlov, Ken Smits, Mark Bohr. 376-377 [doi]
• A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power ManagementHarold Pilo, Vaidyanathan Ramadurai, Geordie Braceras, John Gabric, Steve Lamphier, Yue Tan. 378-379 [doi]
• A High-Density 45nm SRAM Using Small-Signal Non-Strobed Regenerative SensingNaveen Verma, Anantha P. Chandrakasan. 380-381 [doi]
• A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-×-ratio Memory CellAtsushi Kawasumi, Tomoaki Yabe, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Akihito Tohata, Takahiko Sasaki, Akira Katayama, Gou Fukano, Yuki Fujimura, Nobuaki Otsuka. 382-383 [doi]
• 65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOSMasanao Yamaoka, Noriaki Maeda, Yasuhisa Shimazaki, Kenichi Osada. 384-385 [doi]
• A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block RedundancyKyomin Sohn, Young-Ho Suh, Young-Jae Son, Daesik Yim, Kang-Young Kim, Dae-Gi Bae, Ted Kang, Hoon Lim, Soon-Moon Jung, Hyun-Geun Byun, Young-Hyun Jun, Kinam Kim. 386-387 [doi]
• A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOSIk Joon Chang, Jae-Joon Kim, Sang Phill Park, Kaushik Roy. 388-389 [doi]
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• Highlights of IEDM 2007Albert Theuwissen, Roland Thewes, Ernesto Perea. 392-393 [doi]
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• 2 16Gb 4-MLC NAND Flash Memory with 43nm CMOS TechnologyKazushige Kanda, Masaru Koyanagi, Toshio Yamamura, Koji Hosono, Masahiro Yoshihara, Toru Miwa, Yosuke Kato, Alex Mak, Siu Lung Chan, Frank Tsai, Raul Cernea, Binh Le, Eiichi Makino, Takashi Taira, Hiroyuki Otake, Norifumi Kajimura, Susumu Fujimura, Yoshiaki Takeuchi, Mikihiko Itoh, Masanobu Shirakawa, Dai Nakamura, Yuya Suzuki, Yuki Okukawa, Masatsugu Kojima, Kazuhide Yoneya, Takamichi Arizono, Toshiki Hisada, Shinji Miyamoto, Mitsuhiro Noguchi, Toshitake Yaegashi, Masaaki Higashitani, Fumitoshi Ito, Teruhiko Kamei, Gertjan Hemink, Tooru Maruyama, Kazumi Ino, Shigeo Ohshima. 430-431 [doi]
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• An Auto-Selectable-Frequency Pulse-Width Modulator for Buck Converters with Improved Light-Load EfficiencyTsz Yin Man, Philip K. T. Mok, Mansun Chan. 440-441 [doi]
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• A 90nm CMOS Dual-Channel Powerline Communication AFE for Homeplug AV with a Gb ExtensionKeith Findlater, Toby Bailey, Adria Bofill, Neil Calder, Seyed Danesh, Robert K. Henderson, William Holland, Jed Hurwitz, Steven Maughan, Alasdair Sutherland, Ewan Watt. 464-465 [doi]
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• A 0.7V 36μW 85dB-DR Audio ΔΣ Modulator Using Class-C InverterYoungcheol Chae, Inhee Lee, Gunhee Han. 490-491 [doi]
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• A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline StructureKi Tae Park, Doo-Gon Kim, Soonwook Hwang, Myounggon Kang, Hoosung Cho, Youngwook Jeong, Yong-ll Seo, Jae-Hoon Jang, Hansoo Kim, Soon-Moon Jung, Yeong-Taek Lee, Changhyun Kim, Won-Seong Lee. 510-511 [doi]
• A Resonant Global Clock Distribution for the Cell Broadband-Engine ProcessorSteven C. Chan, Phillip Restle, Thomas J. Bucelot, Steve Weitzel, John M. Keaty, John S. Liberty, Brian K. Flachs, Richard Volant, Peter Kapusta, Jeffrey S. Zimmerman. 512-513 [doi]
• A Low-Jitter 8-to-10GHz Distributed DLL for Multiple-Phase Clock GenerationKeng-Jan Hsiao, Tai-Cheng Lee. 514-515 [doi]
• A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOSAlexander Rylyakov, José A. Tierno, Didem Zeliha Turker, Jean-Olivier Plouchart, Herschel A. Ainspan, Daniel J. Friedman. 516-517 [doi]
• A 9.5GHz 6ps-Skew Space-Filling-Curve Clock Distribution with 1.8V Full-Swing Standing-Wave OscillatorsMamoru Sasaki. 518-519 [doi]
• A 2.4GHz MEMS-Based TransceiverDavid Ruffieux, Jérémie Chabloz, Claude Muller, Franz-Xaver Pengg, Paola Tortori, Alexandre Vouilloz. 522-523 [doi]
• A 2GHz 52 μW Wake-Up Receiver with -72dBm Sensitivity Using Uncertain-IF ArchitectureNathan Pletcher, Simone Gambini, Jan M. Rabaey. 524-525 [doi]
• A Fully-Integrated UHF Receiver with Multi-Resolution Spectrum-Sensing (MRSS) Functionality for IEEE 802.22 Cognitive-Radio ApplicationsJongmin Park, Taejoong Song, Joonhoi Hur, Sang Min Lee, Jungki Choi, Kihong Kim, Jungsuk Lee, Kyutae Lim, Chang-Ho Lee, Haksun Kim, Joy Laskar. 526-527 [doi]
• Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave FrequenciesPiet Wambacq, Abdelkarim Mercha, Karen Scheir, Bob Verbruggen, Jonathan Borremans, Vincent De Heyn, Steven Thijs, Dimitri Linten, Geert Van der Plas, Bertrand Parvais, Morin Dehan, Stefaan Decoutere, Charlotte Soens, Nadine Collaert, Malgorzata Jurczak. 528-529 [doi]
• Digital Detection of Oxide Breakdown and Life-Time Extension in Submicron CMOS TechnologyMustafa Acar, Anne-Johan Annema, Bram Nauta. 530-531 [doi]
• Superconductive Single-Flux-Quantum Circuit/System Technology and 40Gb/s Switch System DemonstrationYoshihito Hashimoto, Shuichi Nagasawa, Tetsuro Satoh, Kenji Hinode, Hideo Suzuki, Toshiyuki Miyazaki, Mutsuo Hidaka, Nobuyuki Yoshikawa, Hirotaka Terai, Akira Fujimaki. 532-533 [doi]
• A Wireless Dual-Link System for Sensor Network ApplicationsTohru Kimura, Hitoshi Yano, Yuuichi Aoki, Nobuhide Yoshida, Jun Noda, Teruki Sukenari, Yusuke Konishi, Toshiyasu Nakao, Akitake Mitsuhashi, Daigo Taguchi. 534-535 [doi]
• A 400 μW 4.7-to-6.4GHz VCO under an Above-IC Inductor in 45nm CMOSJonathan Borremans, Piet Wambacq, Maarten Kuijk, Geert Carchon, Stefaan Decoutere. 536-537 [doi]
• An Over-60dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp with 30dB Loop GainB. Robert Gregoire, Un-Ku Moon. 540-541 [doi]
• A 32mW 1.25GS/s 6b 2b/step SAR ADC in 0.13μm CMOSZhiheng Cao, Shouli Yan, Yunchu Li. 542-543 [doi]
• A 24GS/s 6b ADC in 90nm CMOSPeter Schvan, Jérôme Bach, Chris Falt, Philip Flemke, Robert Gibbins, Yuriy M. Greshishchev, Naim Ben Hamida, Daniel Pollex, John Sitch, Shing-Chi Wang, John Wolczanski. 544-545 [doi]
• A 1V 11b 200MS/s Pipelined ADC with Digital Background Calibration in 65nm CMOSKang-Wei Hsueh, Yu-Kai Chou, Yu-Hsuan Tu, Yi-Fu Chen, Ya-Lun Yang, Hung-Sung Li. 546-547 [doi]
• 90nm 4.7ps-Resolution 0.7-LSB Single-Shot Precision and 19pJ-per-Shot Local Passive Interpolation Time-to-Digital Converter with On-Chip CharacterizationStephan Henzler, Siegmar Koeppe, Winfried Kamp, Hans Mulatz, Doris Schmitt-Landsiedel. 548-549 [doi]
• A Clockless ADC/DSP/DAC System with Activity-Dependent Power Dissipation and No AliasingBob Schell, Yannis P. Tsividis. 550-551 [doi]
• A Split-Load Interpolation-Amplifier-Array 300MS/s 8b Subranging ADC in 90nm CMOSYasuhide Shimizu, Shigemitsu Murayama, Kohei Kudoh, Hiroaki Yatsuda. 552-553 [doi]
• A 6b 0.2-to-0.9V Highly Digital Flash ADC with Comparator RedundancyDenis C. Daly, Anantha P. Chandrakasan. 554-555 [doi]
• TX and RX Front-Ends for 60GHz Band in 90nm Standard Bulk CMOSMasahiro Tanomura, Yasuhiro Hamada, Shuya Kishimoto, Masaharu Ito, Naoyuki Orihashi, Kenichi Maruhashi, Hidenori Shimawaki. 558-559 [doi]
• A 60GHz 1V + 12.3dBm Transformer-Coupled Wideband PA in 90nm CMOSDebopriyo Chowdhury, Patrick Reynaert, Ali M. Niknejad. 560-561 [doi]
• 60 and 77GHz Power Amplifiers in Standard 90nm CMOSToshihide Suzuki, Yoichi Kawano, Masaru Sato, Tatsuya Hirose, Kazukiyo Joshin. 562-563 [doi]
• A Single-Chip WCDMA Envelope Reconstruction LDMOS PA with 130MHz Switched-Mode Power SupplyVincent Pinon, Frederic Hasbani, Alexandre Giry, Denis Pache, Christophe Garnier. 564-565 [doi]
• A 28.6dBm 65nm Class-E PA with Envelope Restoration by Pulse-Width and Pulse-Position ModulationJeffrey S. Walling, Hasnain Lakdawala, Yorgos Palaskas, Ashoke Ravi, Ofir Degani, Krishnamurthy Soumyanath, David J. Allstot. 566-567 [doi]
• An Outphasing Power Amplifier for a Software-Defined Radio TransmitterShervin Moloudi, Koji Takinami, Michael Youssef, Mohyee Mikhemar, Asad A. Abidi. 568-569 [doi]
• A Fully Integrated Quad-Band GSM/GPRS CMOS Power AmplifierIchiro Aoki, Scott Kee, Rahul Magoon, Roberto Aparicio, Florian Bohn, Jeff Zachan, Geoff Hatcher, Donald McClymont, Ali Hajimiri. 570-571 [doi]
• Balanced SiGe PA Module for Multi-Band and Multi-Mode Cellular-Phone ApplicationsAntonino Scuderi, Carmelo Santagati, Michele Vaiana, Francesco Pidalà, Mario Paparo. 572-573 [doi]
• A CMOS Temperature-to-Digital Converter with an Inaccuracy of ± 0.5° C (3/spl sigma)from -55 to 125°CCaspar P. L. van Vroonhoven, Kofi A. A. Makinwa. 576-577 [doi]
• nd-Order ΔΣ Sensor Front-End with Signal Boosting and Offset Compensation for a Capacitive 3-Axis Micro-AccelerometerMika Kämäräinen, Matti Paavola, Mikko Saukoski, Erkka Laulainen, Lauri Koskinen, Marko Kosunen, Kari Halonen. 578-579 [doi]
• A Mode-Matching ΔΣ Closed-Loop Vibratory-Gyroscope Readout Interface with a 0.004°/s/√Hz Noise Floor over a 50Hz BandChinwuba D. Ezekwe, Bernhard E. Boser. 580-581 [doi]
• An RF MEMS Variable Capacitor with Intelligent Bipolar ActuationTamio Ikehashi, Takayuki Miyazaki, Hiroaki Yamazaki, Atsushi Suzuki, Etsuji Ogawa, Shinji Miyano, Tomohiro Saito, Tatsuya Ohguro, Takeshi Miyagi, Yoshiaki Sugizaki, Nobuaki Otsuka, Hideki Shibata, Yoshiaki Toyoshima. 582-583 [doi]
• A Chopper-Stabilized Lateral-BJT-Input Interface in 0.6μm CMOS for Capacitive AccelerometersDongning Zhao, Faisal Zaman, Farrokh Ayazi. 584-585 [doi]
• Single-Chip CMOS Analog Sensor-Conditioning ICs with Integrated Electrically-Adjustable Passive ResistorsLeslie Landsberger, Oleg Grudin, Gennadiy Frolov, Zhengrong Huang, Saed Salman, Tommy Tsang, Mathieu Renaud, Bowei Zhang. 586-587 [doi]
• A 100μW 64×128-Pixel Contrast-Based Asynchronous Binary Vision Sensor for Wireless Sensor NetworksNicola Massari, Massimo Gottardi, Syed A. Jawed. 588-589 [doi]
• A 16×16 CMOS Proton Camera Array for Direct Extracellular Imaging of Hydrogen-Ion ActivityMark J. Milgrew, Mathieu O. Riehle, David R. S. Cumming. 590-591 [doi]
• Short CourseIan Galton, Jonathan Audy, Vadim Ivanov, Stefan Rusu, Seth R. Sanders. 648-649 [doi]
• Embedded Memory Design for Nano-Scale VLSI Systems (Forum)Kevin Zhang. 650-651 [doi]
• Wide Dynamic Range Imaging (Forum)Albert Theuwissen. 652-653 [doi]
• Architectures and Circuit Techniques for Nanoscale RF CMOS (Forum)Stefan Heinen, Francesco Svelto, Jan Craninckx, Mototsugu Hamada, Domine Leenaerts, Chris Rudell. 654-655 [doi]
• Power Systems from the Gigawatt to the Microwatt - Generation, Distribution, Storage and Efficient Use of Energy (Forum)Eugenio Cantatore, Siva Narendra. 656-657 [doi]
• Future of High-Speed Transceivers (Forum)Robert Payne. 658-659 [doi]
• Transistor Variability in Nanometer-Scale Technologies (Forum)Ron Ho. 660-661 [doi]
• Digitally-Assisted RF Circuits (Forum)Andrea Baschirotto. 662-663 [doi]