Kyu-hyoun Kim - researchr alias

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Viewing Publication 1 - 20 from 20

2024

14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoCMonodeep Kar, Joel Silberman, Swagath Venkataramani, Viji Srinivasan, Bruce M. Fleischer, Joshua Rubin, JohnDavid Lancaster, Sae Kyu Lee, Matthew Cohen, Matthew M. Ziegler, Nianzheng Cao, Sandra Woodward, Ankur Agrawal, Ching Zhou, Prasanth Chatarasi, Thomas Gooding, Michael Guillorn, Bahman Hekmatshoartabari, Philip Jacob, Radhika Jain, Shubham Jain, Jinwook Jung, Kyu-hyoun Kim, Siyu Koswatta, Martin Lutz, Alberto Mannari, Abey Mathew, Indira Nair, Ashish Ranjan 0001, Zhibin Ren, Scot Rider, Thomas Roewer, David L. Satterfield, Marcel Schaal, Sanchari Sen, Gustavo Tellez, Hung Tran, Wei Wang 0333, Vidhi Zalani, Jintao Zhang, Xin Zhang 0025, Vinay Shah, Robert M. Senger, Arvind Kumar, Pong-Fei Lu, Leland Chang. isscc 2024: 254-256 [doi]

Mixed-Signal Dot-Product Processor with Switched-Capacitors for Machine LearningKyu-hyoun Kim, Mingu Kang. elinfocom 2024: 1-4 [doi]

2023

A Switched-Capacitor Integer Compute Unit with Decoupled Storage and Arithmetic for Cloud AI Inference in 5nm CMOSAnkur Agrawal, Monodeep Kar, Kyu-hyoun Kim, Sergey V. Rylov, Jinwook Jung, Seiji Munetoh, Kohji Hosokawa, Xin Zhang, Bahman Hekmatshoartabari, Fabio Carta, Martin Cochet, Robert Casatuta, Mingu Kang, Sunil Shukla, Kailash Gopalakrishnan, Leland Chang. vlsit 2023: 1-2 [doi]

2022

A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware ThrottlingSae Kyu Lee, Ankur Agrawal, Joel Silberman, Matthew M. Ziegler, Mingu Kang, Swagath Venkataramani, Nianzheng Cao, Bruce M. Fleischer, Michael Guillorn, Matthew Cohen, Silvia M. Mueller, Jinwook Oh, Martin Lutz, Jinwook Jung, Siyu Koswatta, Ching Zhou, Vidhi Zalani, Monodeep Kar, James Bonanno, Robert Casatuta, Chia-Yu Chen, Jungwook Choi, Howard Haynie, Alyssa Herbert, Radhika Jain, Kyu-hyoun Kim, Yulong Li, Zhibin Ren, Scot Rider, Marcel Schaal, Kerstin Schelm, Michael Scheuermann, Xiao Sun, Hung Tran, Naigang Wang, Wei Wang 0333, Xin Zhang 0025, Vinay Shah, Brian W. Curran, Vijayalakshmi Srinivasan, Pong-Fei Lu, Sunil Shukla, Kailash Gopalakrishnan, Leland Chang. jssc, 57(1):182-197, 2022. [doi]

2021

Session 25 Overview: DRAM Memory SubcommitteeDong Uk Lee, Bor-Doou Rong, Kyu-hyoun Kim. isscc 2021: 342-343 [doi]

RaPiD: AI Accelerator for Ultra-low Precision Training and InferenceSwagath Venkataramani, Vijayalakshmi Srinivasan, Wei Wang, Sanchari Sen, Jintao Zhang, Ankur Agrawal, Monodeep Kar, Shubham Jain, Alberto Mannari, Hoang Tran, Yulong Li, Eri Ogawa, Kazuaki Ishizaki, Hiroshi Inoue, Marcel Schaal, Mauricio J. Serrano, Jungwook Choi, Xiao Sun, Naigang Wang, Chia-Yu Chen, Allison Allain, James Bonanno, Nianzheng Cao, Robert Casatuta, Matthew Cohen, Bruce M. Fleischer, Michael Guillorn, Howard Haynie, Jinwook Jung, Mingu Kang, Kyu-hyoun Kim, Siyu Koswatta, Sae Kyu Lee, Martin Lutz, Silvia Mueller, Jinwook Oh, Ashish Ranjan, Zhibin Ren, Scot Rider, Kerstin Schelm, Michael Scheuermann, Joel Silberman, Jie Yang, Vidhi Zalani, Xin Zhang, Ching Zhou, Matthew M. Ziegler, Vinay Shah, Moriyoshi Ohara, Pong-Fei Lu, Brian W. Curran, Sunil Shukla, Leland Chang, Kailash Gopalakrishnan. isca 2021: 153-166 [doi]

2020

Temperature Aware Adaptations for Improved Read Reliability in STT-MRAM Memory SubsystemSaravanan Sethuraman, Venkata Kalyan Tavva, Karthick Rajamani, Chitra K. Subramanian, Kyu-hyoun Kim, Hillery C. Hunter, M. B. Srinivas. tcad, 39(12):4635-4644, 2020. [doi]

2018

Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth OverheadsSeokin Hong, Prashant Jayaprakash Nair, Bülent Abali, Alper Buyuktosunoglu, Kyu-hyoun Kim, Michael B. Healy. micro 2018: 326-338 [doi]

2017

Contutto: a novel FPGA-based prototyping platform enabling innovation in the memory subsystem of a server class processorBharat Sukhwani, Thomas Roewer, Charles L. Haymes, Kyu-hyoun Kim, Adam J. McPadden, Daniel M. Dreps, Dean Sanner, Jan van Lunteren, Sameh W. Asaad. micro 2017: 15-26 [doi]

2013

Understanding and mitigating refresh overheads in high-density DDR4 DRAM systemsJanani Mukundan, Hillery C. Hunter, Kyu-hyoun Kim, Jeffrey Stuecheli, José F. Martínez. isca 2013: 48-59 [doi]

2009

2 0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOSKyu-hyoun Kim, Daniel M. Dreps, Frank D. Ferraiolo, Paul W. Coteus, Seongwon Kim, Sergey V. Rylov, Daniel J. Friedman. isscc 2009: 98-99 [doi]

2008

A 2.6mW 370MHz-to-2.5GHz Open-Loop Quadrature Clock GeneratorKyu-hyoun Kim, Paul W. Coteus, Daniel M. Dreps, Seongwon Kim, Sergey V. Rylov, Daniel J. Friedman. isscc 2008: 458-459 [doi]

2007

An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection SchemeKyu-hyoun Kim, Hoeju Chung, Woo-Seop Kim, Moon-Sook Park, Young-Chan Jang, Jinyoung Kim, Hwan-Wook Park, Uksong Kang, Paul W. Coteus, Joo-Sun Choi, Changhyun Kim. jssc, 42(1):193-200, 2007. [doi]

A Second Order Mixed-Mode Charge Pump Scheme for Low Phase/Duty Error and Low Power ConsumptionKyu-hyoun Kim, In-Young Chung. ieicet, 90-C(1):208-211, 2007. [doi]

2006

A 20-gb/s 256-mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitterKyu-hyoun Kim, Young-Soo Sohn, Chan-Kyoung Kim, Moon-Sook Park, Dong-jin Lee, Woo-Seop Kim, Changhyun Kim. jssc, 41(1):127-134, 2006. [doi]

1999

Low-power dynamic termination scheme using NMOS diode clampingDong-Ho Shin, Young-Min Lee, Kyu-hyoun Kim, Kwyro Lee. jssc, 34(8):1171-1175, 1999. [doi]

1998

An 8-bit-resolution, 360-μs write time nonvolatile analog memory based on differentially balanced constant-tunneling-current scheme (DBCS)Kyu-hyoun Kim, Kwyro Lee, Tae-Sung Jung, Kang-Deog Suh. jssc, 33(11):1758-1762, 1998. [doi]

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