Table of Contents

• Banshee: bandwidth-efficient DRAM caching via software/hardware cooperationXiangyao Yu, Christopher J. Hughes, Nadathur Satish, Onur Mutlu, Srinivas Devadas. 1-14 [doi]
• Contutto: a novel FPGA-based prototyping platform enabling innovation in the memory subsystem of a server class processorBharat Sukhwani, Thomas Roewer, Charles L. Haymes, Kyu-hyoun Kim, Adam J. McPadden, Daniel M. Dreps, Dean Sanner, Jan van Lunteren, Sameh W. Asaad. 15-26 [doi]
• Detecting and mitigating data-dependent DRAM failures by exploiting current memory contentSamira Manabi Khan, Chris Wilkerson, Zhe Wang, Alaa R. Alameldeen, Donghyuk Lee, Onur Mutlu. 27-40 [doi]
• Fine-grained DRAM: energy-efficient DRAM for extreme bandwidth systemsMike O'Connor, Niladrish Chatterjee, Donghyuk Lee, John M. Wilson 0002, Aditya Agrawal, Stephen W. Keckler, William J. Dally. 41-54 [doi]
• UDP: a programmable accelerator for extract-transform-load workloads and moreYuanwei Fang, Chen Zou, Aaron J. Elmore, Andrew A. Chien. 55-68 [doi]
• UNFOLD: a memory-efficient speech recognizer using on-the-fly WFST compositionReza Yazdani, Jose-Maria Arnau, Antonio González 0001. 69-81 [doi]
• IDEAL: image denoising acceleratorMostafa Mahmoud, Bojian Zheng, Alberto Delmas Lascorz, Felix Heide, Jonathan Assouline, Paul Boucher, Emmanuel Onzon, Andreas Moshovos. 82-95 [doi]
• Pipelining a triggered processing elementThomas J. Repetti, João Pedro Cerqueira, Martha A. Kim, Mingoo Seok. 96-108 [doi]
• Efficient exception handling support for GPUsIvan Tanasic, Isaac Gelado, Marc Jordà, Eduard Ayguadé, Nacho Navarro. 109-122 [doi]
• Beyond the socket: NUMA-aware GPUsUgljesa Milic, Oreste Villa, Evgeny Bolotin, Akhil Arunkumar, Eiman Ebrahimi, Aamer Jaleel, Alex Ramírez, David W. Nellans. 123-135 [doi]
• Mosaic: a GPU memory manager with application-transparent support for multiple page sizesRachata Ausavarungnirun, Joshua Landgraf, Vance Miller, Saugata Ghose, Jayneel Gandhi, Christopher J. Rossbach, Onur Mutlu. 136-150 [doi]
• Regless: just-in-time operand staging for GPUsJohn Kloosterman, Jonathan Beaumont, D. Anoushe Jamshidi, Jonathan Bailey, Trevor N. Mudge, Scott A. Mahlke. 151-164 [doi]
• SCRATCH: an end-to-end application-aware soft-GPGPU architecture and trimming toolPedro Duarte, Pedro Tomás, Gabriel Falcão. 165-177 [doi]
• Proteus: a flexible and fast software supported hardware logging approach for NVMSeunghee Shin, Satish Kumar Tirukkovalluri, James Tuck, Yan Solihin. 178-190 [doi]
• Efficient support of position independence on non-volatile memoryGuoyang Chen, Lei Zhang, Richa Budhiraja, Xipeng Shen, Youfeng Wu. 191-203 [doi]
• Incidental computing on IoT nonvolatile processorsKaisheng Ma, Xueqing Li, Jinyang Li, Yongpan Liu, Yuan Xie 0001, Jack Sampson, Mahmut Taylan Kandemir, Vijaykrishnan Narayanan. 204-218 [doi]
• Summarizer: trading communication with computing near storageGunjae Koo, Kiran Kumar Matam, Te I, H. V. Krishna Giri Narra, Jing Li, Hung-Wei Tseng, Steven Swanson, Murali Annavaram. 219-231 [doi]
• Memory cocktail therapy: a general learning-based framework to optimize dynamic tradeoffs in NVMsZhaoxia Deng, Lunkai Zhang, Nikita Mishra, Henry Hoffmann, Frederic T. Chong. 232-244 [doi]
• A many-core architecture for in-memory data processingSandeep R. Agrawal, Sam Idicula, Arun Raghavan, Evangelos Vlachos, Venkatraman Govindaraju, Venkatanathan Varadarajan, Cagri Balkesen, Georgios Giannikis, Charlie Roth, Nipun Agarwal, Eric Sedlar. 245-258 [doi]
• Cache automatonArun Subramaniyan 0001, Jingcheng Wang, Ezhil R. M. Balasubramanian, David Blaauw, Dennis Sylvester, Reetuparna Das. 259-272 [doi]
• Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technologyVivek Seshadri, Donghyuk Lee, Thomas Mullins, Hasan Hassan, Amirali Boroumand, Jeremie Kim, Michael A. Kozuch, Onur Mutlu, Phillip B. Gibbons, Todd C. Mowry. 273-287 [doi]
• DRISA: a DRAM-based reconfigurable in-situ acceleratorShuangchen Li, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Yuan Xie. 288-301 [doi]
• Pageforge: a near-memory content-aware page-merging architectureDimitrios Skarlatos, Nam Sung Kim, Josep Torrellas. 302-314 [doi]
• RHMD: evasion-resilient hardware malware detectorsKhaled N. Khasawneh, Nael B. Abu-Ghazaleh, Dmitry Ponomarev, Lei Yu. 315-327 [doi]
• Software-based gate-level information flow security for IoT systemsHari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar 0002, John Sartori. 328-340 [doi]
• How secure is your cache against side-channel attacks?Zecheng He, Ruby B. Lee. 341-353 [doi]
• Constructing and characterizing covert channels on GPGPUsHoda Naghibijouybari, Khaled N. Khasawneh, Nael B. Abu-Ghazaleh. 354-366 [doi]
• Scale-out acceleration for machine learningJongse Park, Hardik Sharma, Divya Mahajan, Joon Kyung Kim, Preston Olds, Hadi Esmaeilzadeh. 367-381 [doi]
• Bit-pragmatic deep neural network computingJorge Albericio, Alberto Delmas, Patrick Judd, Sayeh Sharify, Gerard O'Leary, Roman Genov, Andreas Moshovos. 382-394 [doi]
• CirCNN: accelerating and compressing deep neural networks using block-circulant weight matricesCaiwen Ding, Siyu Liao, Yanzhi Wang, Zhe Li 0001, Ning Liu, Youwei Zhuo, Chao Wang, Xuehai Qian, Yu Bai, Geng Yuan, Xiaolong Ma, Yipeng Zhang, Jian Tang, Qinru Qiu, Xue Lin, Bo Yuan. 395-408 [doi]
• Using branch predictors to predict brain activity in brain-machine implantsAbhishek Bhattacharjee. 409-422 [doi]
• Load value prediction via path-based address prediction: avoiding mispredictions due to conflicting storesRami Sheikh, Harold W. Cain, Raguram Damodaran. 423-435 [doi]
• Multiperspective reuse predictionDaniel A. Jiménez, Elvira Teran. 436-448 [doi]
• CSALT: context switch aware large TLBYashwant Marathe, Nagendra Gulur, Jee Ho Ryoo, Shuang Song, Lizy K. John. 449-462 [doi]
• RTLcheck: verifying the memory consistency of RTL designsYatin A. Manerkar, Daniel Lustig, Margaret Martonosi, Michael Pellauer. 463-476 [doi]
• Architecting hierarchical coherence protocols for push-button parametric verificationOpeoluwa Matthews, Daniel J. Sorin. 477-489 [doi]
• PARSNIP: performant architecture for race safety with no impact on precisionYuanfeng Peng, Benjamin P. Wood, Joseph Devietti. 490-502 [doi]
• Harnessing voltage margins for energy efficiency in multicore CPUsGeorge Papadimitriou, Manolis Kaliorakis, Athanasios Chatzidimitriou, Dimitris Gizopoulos, Peter Lawthers, Shidhartha Das. 503-516 [doi]
• Race-to-sleep + content caching + display caching: a recipe for energy-efficient video streaming on handheldsHaibo Zhang, Prasanna Venkatesh Rengasamy, Shulin Zhao, Nachiappan Chidambaram Nachiappan, Anand Sivasubramaniam, Mahmut T. Kandemir, Ravi Iyer, Chita R. Das. 517-531 [doi]
• BVF: enabling significant on-chip power savings via bit-value-favor for throughput processorsAng Li, Wenfeng Zhao, Shuaiwen Leon Song. 532-545 [doi]
• Xylem: enhancing vertical thermal conduction in 3D processor-memory stacksAditya Agrawal, Josep Torrellas, Sachin Idgunji. 546-559 [doi]
• Unleashing the power of GPU for physically-based rendering via dynamic ray shufflingYa-shuai Lü, Libo Huang, Li Shen, Zhiying Wang. 560-573 [doi]
• GPUpd: a fast and scalable multi-GPU architecture using cooperative projection and distributionYoungsok Kim, Jae-Eon Jo, Hanhwi Jang, Minsoo Rhu, Hanjun Kim, Jangwoo Kim. 574-586 [doi]
• Versapipe: a versatile programming framework for pipelined computing on GPUZhen Zheng, Chanyoung Oh, Jidong Zhai, Xipeng Shen, Youngmin Yi, Wenguang Chen. 587-599 [doi]
• Wireframe: supporting data-dependent parallelism through dependency graph execution in GPUsAmir Ali Abdolrashidi, Devashree Tripathy, Mehmet Esat Belviranli, Laxmi Narayan Bhuyan, Daniel Wong 0001. 600-611 [doi]
• Schedtask: a hardware-assisted task schedulerPrathmesh Kallurkar, Smruti R. Sarangi. 612-624 [doi]
• Exploiting heterogeneity for tail latency and energy efficiencyMd E. Haque, Yuxiong He, Sameh Elnikety, Thu D. Nguyen, Ricardo Bianchini, Kathryn S. McKinley. 625-638 [doi]
• TMI: thread memory isolation for false sharing repairChristian DeLozier, Ariel Eizenberg, Shiliang Hu, Gilles Pokam, Joseph Devietti. 639-650 [doi]
• Estimating and understanding architectural riskWeilong Cui, Timothy Sherwood. 651-664 [doi]
• Hybrid analog-digital solution of nonlinear partial differential equationsYipeng Huang, Ning Guo, Mingoo Seok, Yannis P. Tsividis, Kyle T. Mandli, Simha Sethumadhavan. 665-678 [doi]
• Taming the instruction bandwidth of quantum computers via hardware-managed error correctionSwamit S. Tannu, Zachary A. Myers, Prashant J. Nair, Douglas M. Carmean, Moinuddin K. Qureshi. 679-691 [doi]
• Optimized surface code communication in superconducting quantum computersAli JavadiAbhari, Pranav Gokhale, Adam Holmes, Diana Franklin, Kenneth R. Brown, Margaret Martonosi, Frederic T. Chong. 692-705 [doi]
• Architectural tradeoffs for biodegradable computingTing-Jung Chang, Zhuozhi Yao, Paul J. Jackson, Barry P. Rand, David Wentzlaff. 706-717 [doi]
• Improving the effectiveness of searching for isomorphic chains in superword level parallelismJoonmoo Huh, James Tuck. 718-729 [doi]
• Data movement aware computation partitioningXulong Tang, Orhan Kislal, Mahmut T. Kandemir, Mustafa Karaköy. 730-744 [doi]
• Mirage cores: the illusion of many out-of-order cores using in-order hardwareShruti Padmanabha, Andrew Lukefahr, Reetuparna Das, Scott A. Mahlke. 745-758 [doi]
• Using intra-core loop-task accelerators to improve the productivity and performance of task-based parallel programsJi Kim, Shunning Jiang, Christopher Torng, Moyang Wang, Shreesha Srinath, Berkin Ilbeyi, Khalid Al-Hawaj, Christopher Batten. 759-773 [doi]
• Architectural opportunities for novel dynamic EMI shifting (DEMIS)Daphne I. Gorman, Matthew R. Guthaus, Jose Renau. 774-785 [doi]
• DeftNN: addressing bottlenecks for DNN execution on GPUs via synapse vector elimination and near-compute data fissionParker Hill, Animesh Jain, Mason Hill, Babak Zamirai, Chang-Hong Hsu, Michael A. Laurenzano, Scott A. Mahlke, Lingjia Tang, Jason Mars. 786-799 [doi]
• Hardware supported persistent object address translationTiancong Wang, Sakthikumaran Sambasivam, Yan Solihin, James Tuck. 800-812 [doi]
• An experimental microarchitecture for a superconducting quantum processorX. Fu, M. A. Rol, C. C. Bultink, J. van Someren, Nader Khammassi, Imran Ashraf, R. F. L. Vermeulen, J. C. de Sterke, W. J. Vlothuizen, R. N. Schouten, Carmen G. Almudéver, L. DiCarlo, Koen Bertels. 813-825 [doi]