- Vijaya Kumar Purushothaman, Eric A. M. Klumperink, Roel Plompen, Bram Nauta. Low-Power High-Linearity Mixer-First Receiver Using Implicit Capacitive Stacking With 3× Voltage Gain. J. Solid-State Circuits, 57(1):245-259, 2022.
- Sachin Taneja, Viveka Konandur Rajanna, Massimo Alioto. In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security. J. Solid-State Circuits, 57(1):153-166, 2022.
- Siwei Li, Gabriel M. Rebeiz. High Efficiency D-Band Multiway Power Combined Amplifiers With 17.5-19-dBm Psat and 14.2-12.1% Peak PAE in 45-nm CMOS RFSOI. J. Solid-State Circuits, 57(5):1332-1343, 2022.
- Yusuke Oike, Borivoje Nikolic. Guest Editorial Introduction to the Special Issue on the 2021 Symposium on VLSI Circuits. J. Solid-State Circuits, 57(4):983-985, 2022.
- Farhad Bozorgi, Melchiorre Bruccoleri, Elham Rahimi, Matteo Repossi, Francesco Svelto, Andrea Mazzanti. Analog Front End of 50-Gb/s SiGe BiCMOS Opto-Electrical Receiver in 3-D-Integrated Silicon Photonics Technology. J. Solid-State Circuits, 57(1):312-322, 2022.
- Yanbo Zhang, Jin Zhang, Shubin Liu, Ruixue Ding, Yan Zhu 0001, Chi-Hang Chan, Rui Paulo Martins. A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC With Gain and Offset Calibrations. J. Solid-State Circuits, 57(3):745-756, 2022.
- Yizhak Shifman, Inbal Stanger, Netanel Shavit, Ramiro Taco, Alexander Fish, Joseph Shor. A Method for Mitigation of Droop Timing Errors Including a 500 MHz Droop Detector and Dual Mode Logic. J. Solid-State Circuits, 57(2):596-608, 2022.
- Mansour Taghadosi, Hossein Kassiri. A Calibration-Free Energy-Efficient IC for Link-Adaptive Real-Time Energy Storage Optimization of CM Inductive Power Receivers. J. Solid-State Circuits, 57(3):793-802, 2022.
- Guillaume Tochou, Robin Benarrouch, David Gaidioz, Andreia Cathelin, Antoine Frappé, Andreas Kaiser, Jan M. Rabaey. A Sub-100-μW 0.1-to-27-Mb/s Pulse-Based Digital Transmitter for the Human Intranet in 28-nm FD-SOI CMOS. J. Solid-State Circuits, 57(5):1409-1420, 2022.
- Jaegeun Song, Yunsoo Park, Chaegang Lim, Yohan Choi, Soonsung Ahn, Sooho Park, Chulwoo Kim. A 9-bit 500-MS/s 2-bit/cycle SAR ADC With Error-Tolerant Interpolation Technique. J. Solid-State Circuits, 57(5):1492-1503, 2022.