Joel Silberman - researchr alias

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Viewing Publication 1 - 23 from 23

2025

Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoCMonodeep Kar, Joel Silberman, Swagath Venkataramani, Viji Srinivasan, Bruce M. Fleischer, Joshua Rubin, JohnDavid Lancaster, Sae Kyu Lee, Matthew Cohen, Matthew M. Ziegler, Nianzheng Cao, Sandra Woodward, Ankur Agrawal, Ching Zhou, Prasanth Chatarasi, Thomas Gooding, Michael Guillorn, Bahman Hekmatshoartabari, Philip Jacob, Radhika Jain, Shubham Jain, Jinwook Jung, Kyu-hyoun Kim, Siyu Koswatta, Martin Lutz, Alberto Mannari, Abey Mathew, Indira Nair, Ashish Ranjan 0001, Zhibin Ren, Scot Rider, Thomas Röwer, David L. Satterfield, Marcel Schaal, Sanchari Sen, Gustavo Tellez, Hung Tran, Wei Wang 0333, Vidhi Zalani, Jintao Zhang, Xin Zhang 0025, Vinay Shah, Robert M. Senger, Arvind Kumar, Pong-Fei Lu, Leland Chang. jssc, 60(1):49-64, January 2025. [doi]

2024

14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoCMonodeep Kar, Joel Silberman, Swagath Venkataramani, Viji Srinivasan, Bruce M. Fleischer, Joshua Rubin, JohnDavid Lancaster, Sae Kyu Lee, Matthew Cohen, Matthew M. Ziegler, Nianzheng Cao, Sandra Woodward, Ankur Agrawal, Ching Zhou, Prasanth Chatarasi, Thomas Gooding, Michael Guillorn, Bahman Hekmatshoartabari, Philip Jacob, Radhika Jain, Shubham Jain, Jinwook Jung, Kyu-hyoun Kim, Siyu Koswatta, Martin Lutz, Alberto Mannari, Abey Mathew, Indira Nair, Ashish Ranjan 0001, Zhibin Ren, Scot Rider, Thomas Roewer, David L. Satterfield, Marcel Schaal, Sanchari Sen, Gustavo Tellez, Hung Tran, Wei Wang 0333, Vidhi Zalani, Jintao Zhang, Xin Zhang 0025, Vinay Shah, Robert M. Senger, Arvind Kumar, Pong-Fei Lu, Leland Chang. isscc 2024: 254-256 [doi]

2022

A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware ThrottlingSae Kyu Lee, Ankur Agrawal, Joel Silberman, Matthew M. Ziegler, Mingu Kang, Swagath Venkataramani, Nianzheng Cao, Bruce M. Fleischer, Michael Guillorn, Matthew Cohen, Silvia M. Mueller, Jinwook Oh, Martin Lutz, Jinwook Jung, Siyu Koswatta, Ching Zhou, Vidhi Zalani, Monodeep Kar, James Bonanno, Robert Casatuta, Chia-Yu Chen, Jungwook Choi, Howard Haynie, Alyssa Herbert, Radhika Jain, Kyu-hyoun Kim, Yulong Li, Zhibin Ren, Scot Rider, Marcel Schaal, Kerstin Schelm, Michael Scheuermann, Xiao Sun, Hung Tran, Naigang Wang, Wei Wang 0333, Xin Zhang 0025, Vinay Shah, Brian W. Curran, Vijayalakshmi Srinivasan, Pong-Fei Lu, Sunil Shukla, Kailash Gopalakrishnan, Leland Chang. jssc, 57(1):182-197, 2022. [doi]

2021

RaPiD: AI Accelerator for Ultra-low Precision Training and InferenceSwagath Venkataramani, Vijayalakshmi Srinivasan, Wei Wang, Sanchari Sen, Jintao Zhang, Ankur Agrawal, Monodeep Kar, Shubham Jain, Alberto Mannari, Hoang Tran, Yulong Li, Eri Ogawa, Kazuaki Ishizaki, Hiroshi Inoue, Marcel Schaal, Mauricio J. Serrano, Jungwook Choi, Xiao Sun, Naigang Wang, Chia-Yu Chen, Allison Allain, James Bonanno, Nianzheng Cao, Robert Casatuta, Matthew Cohen, Bruce M. Fleischer, Michael Guillorn, Howard Haynie, Jinwook Jung, Mingu Kang, Kyu-hyoun Kim, Siyu Koswatta, Sae Kyu Lee, Martin Lutz, Silvia Mueller, Jinwook Oh, Ashish Ranjan, Zhibin Ren, Scot Rider, Kerstin Schelm, Michael Scheuermann, Joel Silberman, Jie Yang, Vidhi Zalani, Xin Zhang, Ching Zhou, Matthew M. Ziegler, Vinay Shah, Moriyoshi Ohara, Pong-Fei Lu, Brian W. Curran, Sunil Shukla, Leland Chang, Kailash Gopalakrishnan. isca 2021: 153-166 [doi]

2020

2018

2016

Thermal analysis of multi-layer functional 3D logic stacksMichael Scheuermann, S. Tian, Raphael Robertazzi, Matthew R. Wordeman, C. Bergeron, H. Jacobson, Phillip Restle, Joel Silberman, Christy Tyberg. 3dic 2016: 1-4 [doi]

2012

A 3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon viasMatt Wordeman, Joel Silberman, Gary Maier, Michael Scheuermann. isscc 2012: 186-187 [doi]

2007

2005

Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell ProcessorToru Asano, Joel Silberman, Sang H. Dhong, Osamu Takahashi, Michael White, Scott R. Cottier, Takaaki Nakazato, Atsushi Kawasumi, Hiroshi Yoshihara. micro, 25(5):30-38, 2005. [doi]

Reducing Power Consumption during TLB Lookups in a PowerPC Embedded ProcessorShivakumar Swaminathan, Sanjay B. Patel, James Dieffenderfer, Joel Silberman. isqed 2005: 54-58 [doi]

Power-Conscious Design of the Cell Processor s Synergistic Processor ElementOsamu Takahashi, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Joel Silberman. micro, 25(5):10-18, 2005. [doi]

The circuit design of the synergistic processor element of a CELL processorOsamu Takahashi, Russ Cook, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Hwa-Joon Oh, S. Onish, Juergen Pille, Joel Silberman. iccad 2005: 111-117

2000

1999

A 1-GHz logic circuit family with sense amplifiersOsamu Takahashi, Naoaki Aoki, Joel Silberman, Sang H. Dhong. jssc, 34(5):616-622, 1999. [doi]

1998

High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz MicroprocessorDavid F. Heidel, Sang H. Dhong, H. Peter Hofstee, Michael Immediato, Kevin J. Nowka, Joel Silberman, Kevin G. Stawiasz. vts 1998: 234-238 [doi]

Designing for a gigahertz [guTS integer processor]H. Peter Hofstee, Sang H. Dhong, David Meltzer, Kevin J. Nowka, Joel Silberman, Jeffrey L. Burns, Stephen D. Posluszny, Osamu Takahashi. micro, 18(3):66-74, 1998. [doi]

Design methodology for a 1.0 GHz microprocessorStephen D. Posluszny, N. Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Uttam Ghoshal, H. Peter Hofstee, David P. LaPotin, K. Lee, D. Meltzer, Hung C. Ngo, Kevin J. Nowka, Joel Silberman, Osamu Takahashi, Ivan Vo. In ICCD. 1998: 17-23 [doi]

A 690 ps read-access latency register file for a GHz integer microprocessorOsamu Takahashi, Joel Silberman, Sang H. Dhong, H. Peter Hofstee, N. Aoki. In ICCD. 1998: 6-10 [doi]

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