Abstract is missing.
- ReflectionsLaura Chizuko Fujino. 4 [doi]
- Remembrances of Dave PricerKenneth C. Smith, Laura Chizuko Fujino. 5 [doi]
- Foreword Integrated Intelligence is the Future of SystemsMakoto Ikeda. 6 [doi]
- Session 1 Overview Plenary Session - Invited PapersKevin Zhang, Makoto Ikeda. 7-8 [doi]
- 1.1 Unleashing the Future of InnovationMark Liu. 9-16 [doi]
- Adaptive Intelligence in The New Computing EraVictor Peng. 17-21 [doi]
- 1.3 Working at the Intersection of Machine Learning, Signal Processing, Sensors, and CircuitsDina Katabi. 26-29 [doi]
- 1.4 There's More to the Picture Than Meets the Eye*, and in the future it will only become more soAlbert Theuwissen. 30-35 [doi]
- Session 2 Overview: Highlighted Chip Releases: 5G and Radar Systems Invited PapersTheodoros Georgantas, Yves Baeyens, Alice Wang. 36-37 [doi]
- 2.1 mm-Wave 5G Radios: Baseband to WavesAhmed Khalil, Islam A. Eshrah, Amr Elsherief, Ahmed Hesham Mehana, Mohamed Abdalla, Mohamed Mobarak, John Kilpatrick, Brian Hall, Ahmed Ashry, Hossam Fahmy, Sherif Salim, Russell Kernan, Brian Herdeg, Gary Sapia, Mohamed El-Nozahi, Mohamed Weheiba, Mark D'Amato, Christian Bautista, Kasey Chatzopoulos, Ahmed Ghoniem, Yossif Mosa, Daniel Roll, Kerem Ok. 38-40 [doi]
- High-Performance and Small Form-Factor mm-Wave CMOS Radars for Automotive and Industrial Sensing in 76-to-81GHz and 57-to-64GHz BandsKrishnanshu Dandu, Sreekiran Samala, Karan Bhatia, Meysam Moallem, Karthik Subburaj, Zeshan Ahmad, Daniel Breen, Sunhwan Jang, Tim Davis, Mayank Singh 0010, Shankar Ram, Vashishth Dudhia, Marc DeWilde, Dheeraj Shetty, John Samuel 0004, Zahir Parkar, Cathy Chi, Pilar Loya, Zachary Crawford, John Herrington, Ross Kulak, Abhinav Daga, Rakesh Raavi, Ravi Teja, Rajesh Veettil, Daniel Khemraj, Indu Prathapan, Prakash Narayanan, Naveen Narayanan, Sangamesh Anandwade, Jasbir Singh, Venkatesh Srinivasan, Neeraj Nayak, Karthik Ramasubramanian, Brian P. Ginsburg, Vijay Rentala. 39-41 [doi]
- SOLI: A Tiny Device for a New Human Machine InterfaceSaverio Trotta, Dave Weber, Reinhard W. Jungmaier, Ashutosh Baheti, Jaime Lien, Dennis Noppeney, Maryam Tabesh, Christoph Rumpler, Michael Aichner, Siegfried Albel, Jagjit S. Bal, Ivan Poupyrev. 42-44 [doi]
- Session 3 Overview: Highlighted Chip Releases: Modern Digital SoCs Invited PapersThomas Burd, Rangharajan Venkatesan, Dennis Sylvester. 44-45 [doi]
- XBOX Series X: A Next-Generation Gaming Console SoCPaul Paternoster, Andy Maki, Andres Hernandez, Mark Grossman, Michael Lau, David Sutherland, Aditya Mathad. 46-48 [doi]
- 3.2 The A100 Datacenter GPU and Ampere ArchitectureJack Choquette, M.-J. Edward Lee, Ronny Krashinsky, Vishnu Balan, Brucek Khailany. 48-50 [doi]
- Kunlun: A 14nm High-Performance AI Processor for Diversified WorkloadsJian Ouyang, Xueliang Du, Yin Ma, Jiaqiang Liu. 50-51 [doi]
- Session 4 Overview: Processors Digital Architectures and Systems SubcommitteeSanu Mathew, Shidhartha Das, Hugh Mair. 52-53 [doi]
- A 7nm 5G Mobile SoC Featuring a 3.0GHz Tri-Gear Application Processor SubsystemHsinChen Chen, Rolf Lagerquist, Ashish Nayak, Hugh Mair, Gokulakrishnan Manoharan, Ericbill Wang, Gordon Gammie, Efron Ho, Anand Rajagopalan, Lee-Kee Yong, Ramu Madhavaram, Madhur Jagota, Chi-Jui Chung, Sudhakar Maruthi, Jenny Wiedemeier, Tao Chen, Henry Hsieh, Daniel Dia, Amjad Sikiligiri, Manzur Rahman, Barry Chen, Curtis Lin, Vincent Lin, Elly Chiang, Cheng-Yuh Wu, Po-Yang Hsu, Jason Tsai, Wade Wu, Achuta Thippana, S. A. Huang. 54-56 [doi]
- 4.2 A 12nm Autonomous-Driving Processor with 60.4TOPS, 13.8TOPS/W CNN Executed by Task-Separated ASIL D ControlKatsushige Matsubara, Hanno Lieske, Motoki Kimura, Atsushi Nakamura, Manabu Koike, Kazuaki Terashima, Shun Morikawa, Yoshihiko Hotta, Takahiro Irita, Seiji Mochizuki, Hiroyuki Hamasaki, Tatsuya Kamei. 56-58 [doi]
- 4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFETColin Schmidt 0001, John Charles Wright, Zhongkai Wang, Eric Chang, Albert J. Ou, Woo-Rham Bae, Sean Huang, Anita Flynn, Brian C. Richards, Krste Asanovic, Elad Alon, Borivoje Nikolic. 58-60 [doi]
- 4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep ModeDavide Rossi, Francesco Conti 0001, Manuel Eggimann, Stefan Mach, Alfio Di Mauro, Marco Guermandi, Giuseppe Tagliavini, Antonio Pullini, Igor Loi, Chen Jie, Eric Flamand, Luca Benini. 60-62 [doi]
- 4.5 BioAIP: A Reconfigurable Biomedical AI Processor with Adaptive Learning for Versatile Intelligent Health MonitoringJiahao Liu, Zhen Zhu, Yong Zhou, Ning Wang, Guanghai Dai, Qingsong Liu, Jianbiao Xiao, Yuxiang Xie, Zirui Zhong, Hongduo Liu, Liang Chang, Jun Zhou 0017. 62-64 [doi]
- 4.6 A 144Kb Annealing System Composed of 9× 16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization ProblemsTakashi Takemoto, Kasho Yamamoto, Chihiro Yoshimura, Masato Hayashi, Masafumi Tada, Hiroaki Saito, Mayumi Mashimo, Masanao Yamaoka. 64-66 [doi]
- 4.7 A 91mW 90fps Super-Resolution Processor for Full HD ImagesHsueh-Yen Shen, Yu-Chi Lee, Tzu-Wei Tong, Chia-Hsiang Yang. 66-68 [doi]
- 4.8 An Area and Energy Efficient 0.12nJ/Pixel 8K 30fps AV1 Video Decoder in 5nm CMOS ProcessTae Sung Kim, Seokhyun Lee, Kyungkoo Lee, Sunyoung Shin, SeungSick Jun, Yongmi Lee, Seungyong Lee 0004, Homin Kang, Changhyun Yim, Yohan Lim, Eikyung Moon, SukHwan Lim, Kyung-Ah Jeong, Inyup Kang. 68-70 [doi]
- Session 5 Overview: Analog Interfaces Analog SubcommitteeJens Anders, Taeik Kim, David T. Blaauw. 70-71 [doi]
- 2 CMOS Humidity Sensor Using Adaptive Range-Shift Zoom CDC and Power-Aware Floating Inverter Amplifier ArrayHeyi Li, Zhichao Tan, Yuanxin Bao, Han Xiao, Hao Zhang, Kaixuan Du, Yihan Zhang, Le Ye, Ru Huang. 72-74 [doi]
- Capacitance-to-Digital Converter for Operation Under Uncertain Harvested Voltage down to 0.3V with No Trimming, Reference and Voltage RegulationOrazio Aiello, Paolo Crovetti, Massimo Alioto. 74-76 [doi]
- 2 Resistor-Based Temperature Sensor with a 1-Point Trimmed Inaccuracy of ± 1.3 ° C (3 σ) from -55 ° C to 125 ° C in 65nm CMOSJan A. Angevare, Youngcheol Chae, Kofi A. A. Makinwa. 76-78 [doi]
- 5.4 A Hybrid Thermal-Diffusivity/Resistor-Based Temperature Sensor with a Self-Calibrated Inaccuracy of ±0.25° C(3 Σ) from -55°C to 125°CSining Pan, Jan A. Angevare, Kofi A. A. Makinwa. 78-80 [doi]
- A 770 kS/s Duty-Cycled Integrated-Fluxgate Magnetometer for Contactless Current SensingPreet Garcha, Viola Schaffer, Baher Haroun, Srinath Ramaswamy, Jim Wieser, Jeffrey Lang, Anantha Chandrakasan. 80-82 [doi]
- A 25A Hybrid Magnetic Current Sensor with 64mA Resolution, 1.8MHz Bandwidth, and a Gain Drift Compensation SchemeAmirhossein Jouyaeian, Qinwen Fan, Mario Motz, Udo Ausserlechner, Kofi A. A. Makinwa. 82-84 [doi]
- 5.7 A MEMS Coriolis Mass Flow Sensor with 300 μ g/h/√Hz Resolution and ± 0.8mg/h Zero StabilityArthur C. de Oliveira, Jarno Groenesteijn, Remco J. Wiegerink, Kofi A. A. Makinwa. 84-86 [doi]
- A 5V Dynamic Class-C Paralleled Single-Stage Amplifier with Near-Zero Dead-Zone Control and Current-Redistributive Rail-to-Rail Gm-Boosting TechniqueSeok-Tae Koh, Ji-Hun Lee, Gyeong-Gu Kang, Hyun-Ki Han, Hyun-Sik Kim. 86-88 [doi]
- Session 6 Overview: High-Performance Receivers and Transmitters for Sub-6GHz Radios Wireless SubcommitteeYiwu Tang, Yuan-Hung Chung, Sudhakar Pamarti. 88-89 [doi]
- 6.1 A Low-Power and Low-Cost 14nm FinFET RFIC Supporting Legacy Cellular and 5G FR1Jongsoo Lee, Byoungioong Kang, Seongwon Joo, Seokwon Lee, Joongho Lee, Seunghoon Kang, lkkyun Jo, Suseop Ahn, Jaeseung Lee, Jeongyeol Bae, Won Ko, Woniun Jung, Sangho Lee, Sangsung Lee, Euiyoung Park, Sungiun Lee, Jeongkyun Woo, Jaehoon Lee, Yanghoon Lee, Kyungmin Lee, Jongwoo Lee, Thomas Byunghak Cho, lnyup Kang. 90-92 [doi]
- 6.2 A 4-Way Doherty Digital Transmitter Featuring 50%-LO Signed IQ Interleave Upconversion with more than 27dBm Peak Power and 40% Drain Efficiency at 10dB Power Back-Off Operating in the 5GHz BandMohammadreza Beikmirza, Yiyu Shen, Mohammadreza Mehrpoo, Mohsen Hashemi, Dieuwert P. N. Mul, Leo C. N. de Vreede, Morteza S. Alavi. 92-94 [doi]
- 6.3 A 0.9V Dual-Channel Filtering-by-Aliasing Receiver Front-End Achieving +35dBm IIP3 and <-81dBm LO Leakage Supporting Intra-and Inter-Band Carrier AggregationShi Bu, Sudhakar Pamarti. 94-96 [doi]
- 6.4 A 1-to-3GHz Co-Channel Blocker Resistant, Spatially and Spectrally Passive MIMO Receiver in 65nm CMOS with +6dBm In-Band/In-Notch B1dBJitesh Poojary, Ramesh Harjani. 96-98 [doi]
- 6.5 A 3dB-NF 160MHz-RF-BW Blocker-Tolerant Receiver with Third-Order Filtering for 5G NR ApplicationsMohammad Ali Montazerolghaem, Sergio Pires, Leo C. N. de Vreede, Masoud Babaie. 98-100 [doi]
- 6.6 Full-Duplex Receiver with Wideband Multi-Domain FIR Cancellation Based on Stacked-Capacitor, N-Path Switched-Capacitor Delay Lines Achieving >54dB SIC Across 80MHz BW and >15dBm TX Power-HandlingAravind Nagulu, Sasank Garikapati, Mostafa Essawy, Igor Kadota, Tingjun Chen, Arun Natarajan, Gil Zussman, Harish Krishnaswamy. 100-102 [doi]
- 29.8 115nA@3V ULPMark-CP Score 1205 SCVR-Less Dynamic Voltage-Stacking Scheme for IoT MCUXiaomin Li, Yibo Xu, Lizheng Ren, Weiwei Ge, Jianlong Cai, Xinning Liu, Jun Yang. 100-102 [doi]
- A 1.75dB-NF 25mW 5GHz Transformer-Based Noise- Cancelling CMOS Receiver Front-EndKaituo Yang, Chirn Chye Boon, Guangyin Feng, Chenyang Li, Zhe Liu, Ting Guo, Xiang Yi, Yangtao Dong, Ao Zhou, Xiaoying Wang. 102-104 [doi]
- Session 7 Overview: Imagers and Range Sensors Imagers, Medical, Mems and Displays SubcommitteeVyshnavi Suntharalingam, Calvin Yi-Ping Chao, Bruce Rae. 104-105 [doi]
- A 4-tap 3.5 μm 1.2 Mpixel Indirect Time-of-Flight CMOS Image Sensor with Peak Current Mitigation and Multi-User Interference CancellationMin-Sun Keel, Daeyun Kim, Yeomyung Kim, Myunghan Bae, Myoungoh Ki, Bumsik Chung, Sooho Son, Hoyong Lee, Heeyoung Jo, Seung-chul Shin, Sunjoo Hong, Jaeil An, Yonghun Kwon, Sungyoung Seo, Sunghyuck Cho, Youngchan Kim, Young-Gu Jin, Youngsun Oh, Yitae Kim, JungChak Ahn, Kyoungmin Koh, Yongin Park. 106-108 [doi]
- 7.2 A 48 ×4013.5 mm Depth Resolution Flash LiDAR Sensor with In-Pixel Zoom Histogramming Time-to-Digital ConverterBumjun Kim, Seonghyeok Park, Jung-Hoon Chun, Jaehyuk Choi, Seong-Jin Kim. 108-110 [doi]
- A 189x600 Back-Illuminated Stacked SPAD Direct Time-of-Flight Depth Sensor for Automotive LiDAR SystemsOichi Kumagai, Junichi Ohmachi, Masao Matsumura, Shinichiro Yagi, Kenichi Tayu, Keitaro Amagawa, Tomohiro Matsukawa, Osamu Ozawa, Daisuke Hirono, Yasuhiro Shinozuka, Ryutaro Homma, Kumiko Mahara, Toshio Ohyama, Yousuke Morita, Shohei Shimada, Takahisa Ueno, Akira Matsumoto, Yusuke Otake, Toshifumi Wakano, Takashi Izawa. 110-112 [doi]
- 7.4 A 256×128 3D-Stacked (45nm) SPAD FLASH LiDAR with 7-Level Coincidence Detection and Progressive Gating for 100m Range and 10klux Background LightPreethi Padmanabhan, Chao Zhang 0019, Marco Cazzaniga, Baris Efe, Augusto Ronchini Ximenes, Myung-Jae Lee, Edoardo Charbon. 111-113 [doi]
- 7.5 A 250fps 124dB Dynamic-Range SPAD Image Sensor Stacked with Pixel-Parallel Photon Counter Employing Sub-Frame Extrapolating Architecture for Motion Artifact SuppressionJun Ogi, Takafumi Takatsuka, Kazuki Hizu, Yutaka Inaoka, Hongbo Zhu, Yasuhisa Tochigi, Yoshiaki Tashiro, Fumiaki Sano, Yusuke Murakawa, Makoto Nakamura, Yusuke Oike. 113-115 [doi]
- 7.6 A High-Speed Back-Illuminated Stacked CMOS Image Sensor with Column-Parallel kT/C-Cancelling S&H and Delta-Sigma ADCChihiro Okada, Koushi Uemura, Luong Hung, Kouji Matsuura, Takashi Moue, Daisuke Yamazaki, Kazutoshi Kodama, Masafumi Okano, Takafumi Morikawa, Kazuyoshi Yamashita, Osamu Oka, Itai Shvartz, Golan Zeituni, Ariel Benshem, Noam Eshel, Yoshiaki Inada. 116-118 [doi]
- A 0.2-to-3.6TOPS/W Programmable Convolutional Imager SoC with In-Sensor Current-Domain Ternary-Weighted MAC Operations for Feature Extraction and Region-of-Interest DetectionMartin Lefebvre, Ludovic Moreau, Rémi Dekimpe, David Bol. 118-120 [doi]
- 7.8 A 1-inch 17Mpixel 1000fps Block-Controlled Coded-Exposure Back-Illuminated Stacked CMOS Image Sensor for Computational Imaging and Adaptive Dynamic Range ControlTomoki Hirata, Hironobu Murata, Hideaki Matsuda, Yojiro Tezuka, Shiro Tsunai. 120-122 [doi]
- 7.9 1/2.74-inch 32Mpixel-Prototype CMOS Image Sensor with 0.64μ m Unit Pixels Separated by Full-Depth Deep-Trench IsolationJongEun Park, Sungbong Park, Kwansik Cho, Taehun Lee, ChangKyu Lee, Donghyun Kim, Beomsuk Lee, SungIn Kim, Ho-Chul Ji, Dongmo Im, Haeyong Park, Jinyoung Kim, Jungho Cha, Tae Hoon Kim, Insung Joe, Soojin Hong, Chongkwang Chang, Jingyun Kim, WooGwan Shim, Taehee Kim, Jamie Lee, Donghyuk Park, Euiyeol Kim, Howoo Park, Jaekyu Lee, Yitae Kim, JungChak Ahn, Youngki Hong, ChungSam Jun, Hyunchul Kim, Chang-Rok Moon, Ho-Kyu Kang. 122-124 [doi]
- Session 8 Overview: Ultra-High-Speed Wireline Wireline SubcommitteeYohan Frans, Patrick Yue, Thomas Toifl. 124-125 [doi]
- 8.1 A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOSJihwan Kim, Sandipan Kundu, Ajay Balankutty, Matthew Beach, Bong Chan Kim, Stephen Kim, Yutao Liu, Savyassachi Keshava Murthy, Priya Wali, Kai Yu, Hyung Seok Kim, Chuanchang Liu, Dongseok Shin, Ariel Cohen 0001, Yongping Fan, Frank O'Mahony. 126-128 [doi]
- 8 An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOSMinsoo Choi, Zhongkai Wang, Kyoungtae Lee, Kwanseo Park, Zhaokai Liu, Ayan Biswas, Jaeduk Han, Elad Alon. 128-130 [doi]
- An 8b DAC-Based SST TX Using Metal Gate Resistors with 1.4pJ/b Efficiency at 112Gb/s PAM-4 and 8-Tap FFE in 7iim CMOSMarcel A. Kossel, Vishal Khatri, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Serdar A. Yonar, Mridula Prathapan, Eric J. Lukes, Raymond A. Richetta, Carrie Cox. 130-132 [doi]
- 8.4 A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2Marc-Andre LaCroix, Euhan Chong, Weilun Shen, Ehud Nir, Faisal Ahmed Musa, Haitao Mei 0002, Mohammad-Mahdi Mohsenpour, Semyon Lebedev, Babak Zamanlooy, Carlos Carvalho, Qian Xin, Dmitry Petrov, Henry Wong, Huong Ho, Yang Xu, Sina Naderi Shahi, Peter Krotnev, Chris Feist, Howard Huang, Davide Tonietto. 132-134 [doi]
- 8.5 A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nmDanfeng Xu, Yu Kou, Paul Lai, Zichuan Cheng, Tze Yin Cheung, Larry Moser, Yang Zhang, Xiaolong Liu, Man Pio Lam, Haikun Jia, Quan Pan, Wing Hong Szeto, Chi Fai Tang, Ka Fai Mak, Khawar Sarfraz, Tairan Zhu, Ming Kwan, Emily Yim Lee Au, Cormac Conroy, Kai-Keung Chan. 134-136 [doi]
- 8.6 A Highly Reconfigurable 40-97GS/s DAC and ADC with 40GHz AFE Bandwidth and Sub-35fJ/conv-step for 400Gb/s Coherent Optical Applications in 7nm FinFETR. L. Nguyen, A. M. Castrillon, A. Fan, A. Mellati, Benjamin T. Reyes, Cindra Abidin, E. Olsen, F. Ahmad, Geoff Hatcher, J. Chana, Laura Biolato, L. Tse, L. Wang, M. Azarmnia, M. Davoodi, N. Campos, N. Fan, P. Prabha, Q. Lu, S. Cyrusian, S. Dallaire, S. Ho, S. Jantzi, T. Dusatko, W. Elsharkasy. 136-138 [doi]
- 8.7 A 112Gb/s ADC-DSP-Based PAM-4 Transceiver for Long-Reach Applications with >40dB Channel Loss in 7nm FinFETP. Mishra, A. Tan, Belal Helal, C. R. Ho, C. Loi, Jamal Riani, J. Sun, Kaizad Mistry, Karthik Raviprakash, L. Tse, M. Davoodi, M. Takefman, N. Fan, P. Prabha, Q. Liu, Q. Wang, Rajasekhar Nagulapalli, S. Cyrusian, S. Jantzi, S. Scouten, T. Dusatko, T. Setya, V. Giridharan, V. Gurumoorthy, Victor Karam, W. Liew, Y. Liao, Y. Ou. 138-140 [doi]
- A 112Gb/s PAM-4 Low-Power 9-Tap Sliding-Block DFE in a 7nm FinFET Wireline ReceiverJames Bailey, Hossein Shakiba, Ehud Nir, Grigory Marderfeld, Peter Krotnev, Marc-Andre LaCroix, David Cassan. 140-142 [doi]
- Session 9 Overview: ML Processors From Cloud to Edge Machine Learning SubcommitteeSukHwan Lim, Luca Benini, Vivienne Sze. 142-143 [doi]
- A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware ThrottlingAnkur Agrawal, Sae Kyu Lee, Joel Silberman, Matthew M. Ziegler, Mingu Kang, Swagath Venkataramani, Nianzheng Cao, Bruce M. Fleischer, Michael Guillorn, Matt Cohen, Silvia Mueller, Jinwook Oh, Martin Lutz, Jinwook Jung, Siyu Koswatta, Ching Zhou, Vidhi Zalani, James Bonanno, Robert Casatuta, Chia-Yu Chen, Jungwook Choi, Howard Haynie, Alyssa Herbert, Radhika Jain, Monodeep Kar, Kyu-hyoun Kim, Yulong Li, Zhibin Ren, Scot Rider, Marcel Schaal, Kerstin Schelm, Michael Scheuermann, Xiao Sun, Hung Tran, Naigang Wang, Wei Wang, Xin Zhang, Vinay Shah, Brian W. Curran, Vijayalakshmi Srinivasan, Pong-Fei Lu, Sunil Shukla, Leland Chang, Kailash Gopalakrishnan. 144-146 [doi]
- 9.2A 28nm 12.1TOPS/W Dual-Mode CNN Processor Using Effective-Weight-Based Convolution and Error-Compensation-Based PredictionHuiyu Mo, Wenping Zhu, Wenjing Hu, Guangbin Wang, Qiang Li, Ang Li, Shouyi Yin, Shaojun Wei, Leibo Liu. 146-148 [doi]
- A 40nm 4.81TFLOPS/W 8b Floating-Point Training Processor for Non-Sparse Neural Networks Using Shared Exponent Bias and 24-Way Fused Multiply-Add TreeJeongwoo Park, SunWoo Lee, Dongsuk Jeon. 148-150 [doi]
- 9.4 PIU: A 248GOPS/W Stream-Based Processor for Irregular Probabilistic Inference Networks Using Precision-Scalable Posit Arithmetic in 28nmNimish Shah, Laura Isabel Galindez Olascoaga, Shirui Zhao, Wannes Meert, Marian Verhelst. 150-152 [doi]
- 9.5 A 6K-MAC Feature-Map-Sparsity-Aware Neural Processing Unit in 5nm Flagship Mobile SoCJun-Seok Park, Jun-Woo Jang, Heonsoo Lee, Dongwoo Lee, Sehwan Lee, Hanwoong Jung, SeungWon Lee, Suknam Kwon, Kyung-Ah Jeong, Joon Ho Song, SukHwan Lim, Inyup Kang. 152-154 [doi]
- 9.6 A 1/2.3inch 12.3Mpixel with On-Chip 4.97TOPS/W CNN Processor Back-Illuminated Stacked CMOS Image SensorRyoji Eki, Satoshi Yamada, Hiroyuki Ozawa, Hitoshi Kai, Kazuyuki Okuike, Hareesh Gowtham, Hidetomo Nakanishi, Edan Almog, Yoel Livne, Gadi Yuval, Eli Zyss, Takashi Izawa. 154-156 [doi]
- 9.7 A 184 µ W Real-Time Hand-Gesture Recognition System with Hybrid Tiny Classifiers for Smart Wearable DevicesYuncheng Lu, Van Loi Le, Tony Tae-Hyoung Kim. 156-158 [doi]
- 2 SoC for IoT Devices with 18ms Noise-Robust Speech-to-Text Latency via Bayesian Speech Denoising and Attention-Based Sequence-to-Sequence DNN Speech Recognition in 16nm FinFETThierry Tambe, En-Yu Yang, Glenn G. Ko, Yuji Chai, Coleman Hooper, Marco Donato, Paul N. Whatmough, Alexander M. Rush, David Brooks 0001, Gu-Yeon Wei. 158-160 [doi]
- A Background-Noise and Process-Variation-Tolerant 109nW Acoustic Feature Extractor Based on Spike-Domain Divisive-Energy Normalization for an Always-On Keyword Spotting DeviceDewei Wang, Sung Justin Kim, Minhao Yang, Aurel A. Lazar, Mingoo Seok. 160-162 [doi]
- Session 10 Overview: Continuous-Time ADCs and DACs Data Converter SubcommitteeSeyfi S. Bazarjani, Jongwoo Lee, Marco Corsi. 162-163 [doi]
- 10.1 A 116μ W 104.4dB-DR 100.6dB-SNDR CT Δ∑ Audio ADC Using Tri-Level Current-Steering DAC with Gate-Leakage Compensated Off-Transistor-Based Bias Noise FilterChilun Lo, Jongmi Lee, Yong Lim, YoungHyun Yoon, Hyunseok Hwang, Jaehoon Lee, Moo-Yeol Choi, Myungjin Lee, Seunghyun Oh, Jongwoo Lee. 164-166 [doi]
- 10.2 A 139 µ W 104.8dB-DR 24 kHz-BW CT ΔΣM with Chopped AC-Coupled OTA-Stacking and FIR DACsSomok Mondal, Omid Ghadami, Drew A. Hall. 166-168 [doi]
- 10.3 A 100MHz-BW 68dB-SNDR Tuning-Free Hybrid-Loop DSM with an Interleaved Bandpass Noise-Shaping SAR QuantizerLu Jie, Hsiang-Wen Chen, Boyi Zheng, Michael P. Flynn. 167-169 [doi]
- 10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SARWei Shi, Jiaxin Liu, Abhishek Mukherjee, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Nan Sun. 170-172 [doi]
- A 12b 600MS/s Pipelined SAR and 2x-Interleaved Incremental Delta-Sigma ADC with Source-Follower-Based Residue-Transfer Scheme in 7nm FinFETSeung-Yeob Baek 0002, Il-Hoon Jang, Michael Choi, Hyungdong Roh, Woongtaek Lim, Youngjae Cho, Jongshin Shin. 172-174 [doi]
- 10.6 A 12b 16GS/s RF-Sampling Capacitive DAC for Multi-Band Soft-Radio Base-Station Applications with On-Chip Transmission-Line Matching Network in 16nm FinFETDaniel Gruber, Martin Clara, Ramon Sanchez, Yu-Shan Wang, Christoph Duller, Gerald Rauter, Patrick Torta, Kamran Azadet. 174-176 [doi]
- 10.7 A 64GS/s 4×-Interpolated 1b Semi-Digital FIR DAC for Wideband Calibration and BIST of RF-Sampling A/D ConvertersMartin Clara, Daniel Gruber, Albert Molina, Matteo Camponeschi, Yu-Shan Wang, Christian Lindholm, Hundo Shin, Ramon Sanchez, Christoph Duller, Patrick Torta, Kamran Azadet. 176-178 [doi]
- Session 11 Overview: Advanced Wireline Links and Techniques Wireline SubcommitteeMike Shuo-Wei Chen, Wei-Zen Chen, Amir Amirkhany. 178-179 [doi]
- 11.1 A 1.7pJ/b 112Gb/s XSR Transceiver for Intra-Package Communication in 7nm FinFET TechnologyRamy Yousry, E.-Hung Chen, Yu-Ming Ying, Mohammed Abdullatif, Mohammad Elbadry, Ahmed ElShater, Tsz-Bin Liu, Joonyeong Lee, Dhinessh Ramachandran, Kaiz Wang, Chih-Hao Weng, Mau-Lin Wu, Tamer Ali. 180-182 [doi]
- 11.2 A 26.5625-to-106.25Gb/s XSR SerDes with 1.55pJ/b Efficiency in 7nm CMOSRavi Shivnaraine, Marcus van Ierssel, Kamran Farzan, Dominic DiClemente, George Ng, Nanyan Wang, Javid Musayev, Gairik Dutta, Masumi Shibata, Arash Moradi, Haleh Vahedi, Manavi Farzad, Prabhnoor Kainth, Matt Yu, Nhat Nguyen, Jennifer Pham, Angus McLaren. 181-183 [doi]
- A 480Gb/s/mm 1.7pJ/b Short-Reach Wireline Transceiver Using Single-Ended NRZ for Die-to-Die ApplicationsKelvin McCollough, Scott D. Huss, James Vandersand, Randall Smith, Chris Moscone, Qazi Omar Farooq. 184-185 [doi]
- 11.4 A High-Accuracy Multi-Phase Injection-Locked 8-Phase 7GHz Clock Generator in 65nm with 7b Phase Interpolators for High-Speed Data LinksZhaowen Wang, Yudong Zhang, Yuka Onizuka, Peter R. Kinget. 186-188 [doi]
- 11.5 A 23.9-to-29.4GHz Digital LC-PLL with a Coupled Frequency Doubler for Wireline Applications in 10nm FinFETDongseok Shin, Hyung Seok Kim, Chuanchang Liu, Priya Wali, Savyasaachi Keshava Murthy, Yongping Fan. 188-190 [doi]
- 11.6 A 100Gb/s-8.3dBm-Sensitivity PAM-4 Optical Receiver with Integrated TIA, FFE and Direct-Feedback DFE in 28nm CMOSHao Li, Jahnavi Sharma, Chun-Ming Hsu, Ganesh Balamurugan, James E. Jaussi. 190-192 [doi]
- 11.7 A 56Gb/s 50mW NRZ Receiver in 28nm CMOSAtharav Atharav, Behzad Razavi. 192-194 [doi]
- An Echo-Cancelling Front-End for 112Gb/s PAM-4 Simultaneous Bidirectional Signaling in 14nm CMOSRamin Farjadrad, Kambiz Kaviani, David Nguyen, Michael Brown, Govert Geelen, Corné Bastiaansen, Narendra Rao, Viswa Popuri, Greg Shen, Hamid Khatibi, Saudas Dey, Anirban Chatterjee, David Shen, Peter Zijlstra, Harrie Gunnink, Kebin Zhang, Venkat Penumuchu, Oliver Weiss, Edward J. F. Paulus, Joost Briaire. 194-196 [doi]
- A 105Gb/s Dielectric-Waveguide Link in 130nm BiCMOS Using Channelized 220-to-335GHz Signal and Integrated Waveguide CouplerJack W. Holloway, Georgios C. Dogiamis, Ruonan Han 0001. 196-198 [doi]
- Session 12 Overview: Innovations in Low-Power and Secure IoT Technology Directions SubcommitteeSriram Vangal, Long Yan, Frederic Gianesello. 198-199 [doi]
- 12.2 Improving the Range of WiFi Backscatter Via a Passive Retro-Reflective Single-Side-Band-Modulating MIMO Array and Non-Absorbing TerminationMiao Meng, Manideep Dunna, Hans Yu, Shihkai Kuo, H. P. P.-Wang, Dinesh Bharadia, Patrick P. Mercier. 202-204 [doi]
- 12.3 Exploring PUF-Controlled PA Spectral Regrowth for Physical-Layer Identification of IoT NodesQiang Zhou, Yan He, Kaiyuan Yang, Taiyun Chi. 204-206 [doi]
- Session 13 Overview: Cryo-CMOS for Quantum Computing Technology Directions SubcommitteeDenis Daly, Shawn S. H. Hsu, Edoardo Charbon. 206-207 [doi]
- A Fully Integrated Cryo-CMOS SoC for Qubit Control in Quantum Computers Capable of State Manipulation, Readout and High-Speed Gate Pulsing of Spin Qubits in Intel 22nm FFL FinFET TechnologyJong Seok Park, Sushil Subramanian, Lester Lampert, Todor Mladenov, Ilya Klotchkov, Dileep Kurian, Esdras Juárez-Hernández, Brando Perez Esparza, Sirisha Rani Kale, K. T. Asma Beevi, Shavindra P. Premaratne, Thomas Watson 0006, Satoshi Suzuki, Mustafijur Rahman, Jaykant Timbadiya, Saksham Soni, Stefano Pellerano. 208-210 [doi]
- A Fully-Integrated 40-nm 5-6.5 GHz Cryo-CMOS System-on-Chip with I/Q Receiver and Frequency Synthesizer for Scalable Multiplexed Readout of Quantum DotsAndrea Ruffino, Yatao Peng, Tsung-Yeh Yang, John Michniewicz, Miguel Fernando Gonzalez-Zalba, Edoardo Charbon. 210-212 [doi]
- A 6-to-8GHz 0.17mW/Qubit Cryo-CMOS Receiver for Multiple Spin Qubit Readout in 40nm CMOS TechnologyBagas Prabowo, Guoji Zheng, Mohammadreza Mehrpoo, Bishnu Patra, Patrick Harvey-Collard, Jurgen Dijkema, Amir Sammak, Giordano Scappucci, Edoardo Charbon, Fabio Sebastiano, Lieven M. K. Vandersypen, Masoud Babaie. 212-214 [doi]
- 13.4 A 1GS/s 6-to-8b 0.5mW/Qubit Cryo-CMOS SAR ADC for Quantum Computing in 40nm CMOSGerd Kiene, Alessandro Catania, Ramon Overwater, Paolo Bruschi, Edoardo Charbon, Masoud Babaie, Fabio Sebastiano. 214-216 [doi]
- Session 14 Overview: mm-Wave Transceivers for Communication and Radar Wireless SubcommitteeBodhisatwa Sadhu, Matteo Bassi, Vito Giannini. 216-217 [doi]
- 14.1 A 71-to-86GHz Packaged 16-Element by 16-Beam Multi-User Beamforming Integrated Receiver in 28nm CMOSEmily Naviasky, Lorenzo Iotti, Greg LaCaille, Borivoje Nikolic, Elad Alon, Ali Niknejad. 218-220 [doi]
- An Early Fusion Complementary RADAR-LiDAR TRX in 65nm CMOS Supporting Gear-Shifting Sub-cm Resolution for Smart Sensing and ImagingLiheng Lou, Kai Tang, Zhongyuan Fang, Yisheng Wang, Bo Chen, Ting Guo, Xiaohua Feng, Siyu Liu, Wensong Wang, Yuanjin Zheng. 220-222 [doi]
- 14.3 A 26GHz Full-Duplex Circulator Receiver with 53UB/400MHz(40UB/800MHz) Self-Interference Cancellation for mm-Wave RepeatersRobin Garg, Sanket Jain, Paul Dania, Arun Nataraian. 222-224 [doi]
- A 24-to-30GHz Double-Quadrature Direct-Upconversion Transmitter with Mutual-Coupling-Resilient Series-Doherty Balanced PA for 5G MIMO ArraysMasoud Pashaeifar, Leo C. N. de Vreede, Morteza S. Alavi. 223-225 [doi]
- 14.5 A 1V W-Band Bidirectional Transceiver Front-End with <1dB T/R Switch Loss, <1°/dB Phase/Gain Resolution and 12.3% TX PAE at 15.1dBm Output Power in 65nm CMOS TechnologyWei Zhu 0004, Jiawen Wang, Ruitao Wang, Yan Wang. 226-228 [doi]
- 14.6 A 76-to-81GHz 2×8 FMCW MIMO Radar Transceiver with Fast Chirp Generation and Multi-Feed Antenna-in-Package ArrayZongming Duan, Bowen Wu, Chuanming Zhu, Yan Wang, Weiwei Jin, Ying Liu, Yanhui Wu, Tao Zhang, Ming Liu, Bingfei Dou, Bingbing Liao, Wei Lv, Dongfang Pan, Yongjie Li, Changwei Wang, Yuefei Dai, Pei Li, Hao Gao. 228-230 [doi]
- 14.7 An Adaptive Analog Temperature-Healing Low-Power 17.7-to-19.2GHz RX Front-End with ±0.005dB/°C Gain Variation, <1.6dB NF Variation, and <2.2dB IP1dB Variation across -15 to 85°C for Phased-Array ReceiverMin Li, Nayu Li, Huiyan Gao, Shaogang Wang, Zijiang Zhang, Peidi Chen, Ningjie Wei, Qun Jane Gu, Chunyi Song, Zhiwei Xu 0003. 230-232 [doi]
- A Fully Integrated 62-to-69GHz Crystal-Less Transceiver with 12 Channels Tuned by a Transmission-Line- Referenced FLL in 0.13µm BiCMOSJaeho Im, Hyeongseok Kim, Omar Abdelatty, David D. Wentzloff. 232-234 [doi]
- Session 15 Overview: Compute-in-Memory Processors for Deep Neural Networks Machine Learning SubcommitteeJun Deguchi, Yongpan Liu, Yan Li. 234-235 [doi]
- A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory ComputingHongyang Jia, Murat Ozatay, Yinqi Tang, Hossein Valavi, Rakshit Pathak, Jinseok Lee, Naveen Verma. 236-238 [doi]
- A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight UpdatingJinshan Yue, Xiaoyu Feng, Yifan He, Yuxuan Huang, Yipeng Wang 0009, Zhe Yuan, Mingtao Zhan, Jiaxin Liu, Jian-Wei Su, Yen-Lin Chung, Ping-Chun Wu, Li-Yang Hung, Meng-Fan Chang, Nan Sun, Xueqing Li, Huazhong Yang, Yongpan Liu. 238-240 [doi]
- 15.3 A 65nm 3T Dynamic Analog RAM-Based Computing-in-Memory Macro and CNN Accelerator with Retention Enhancement, Adaptive Analog Sparsity and 44TOPS/W System Energy EfficiencyZhengyu Chen, Xi Chen, Jie Gu 0001. 240-242 [doi]
- 15.4 A 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity-Based Optimization and Variable-Precision QuantizationRuiqi Guo, Zhiheng Yue, Xin Si, Te Hu, Hao Li, Limei Tang, Yabing Wang, Leibo Liu, Meng-Fan Chang, Qiang Li, Shaojun Wei, Shouyi Yin. 242-244 [doi]
- Session 16 Overview: Computation in Memory Memory SubcommitteeMeng-Fan Chang, Ru Huang, Seung-Jun Bae. 244-245 [doi]
- A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge DevicesCheng-Xin Xue, Je-Min Hung, Hui-Yao Kao, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Peng Chen, Ta-Wei Liu, Chuan-Jia Jhang, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang. 245-247 [doi]
- 16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain ComputingShanshan Xie, Can Ni, Aseem Sayal, Pulkit Jain, Fatih Hamzaoglu, Jaydeep P. Kulkarni. 248-250 [doi]
- 16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge ChipsJian-Wei Su, Yen-Chi Chou, Ruhui Liu, Ta-Wei Liu, Pei-Jung Lu, Ping-Chun Wu, Yen-Lin Chung, Li-Yang Hung, Jin-Sheng Ren, Tianlong Pan, Sih-Han Li, Shih-Chieh Chang, Shyh-Shyuan Sheu, Wei-Chung Lo, Chih-I Wu, Xin Si, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang. 250-252 [doi]
- 2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge ApplicationsYu-Der Chih, Po-Hao Lee, Hidehiro Fujiwara, Yi-Chun Shih, Chia-Fu Lee, Rawan Naous, Yu-Lin Chen, Chieh-Pu Lo, Cheng-Han Lu, Haruki Mori, Wei-Cheng Zhao, Dar Sun, Mahmut E. Sinangil, Yen-Huei Chen, Tan-Li Chou, Kerem Akarvardar, Hung-Jen Liao, Yih Wang, Meng-Fan Chang, Tsung-Yung Jonathan Chang. 252-254 [doi]
- Session 17 Overview: DC-DC Converters Power Management SubcommitteeLi Geng, Harish Krishnamurthy, Gaël Pillonnet. 254-255 [doi]
- A Two-Stage Cascaded Hybrid Switched-Capacitor DC-DC Converter with 96.9% Peak Efficiency Tolerating 0.6V/μs Input Slew Rate During StartupZiyu Xia, Jason T. Stauth. 256-258 [doi]
- 26.3 A mm-Wave Power Amplifier for 5G Communication Using a Dual-Drive Topology Exhibiting a Maximum PAE of 50% and Maximum DE of 60% at 30GHzEdgar Felipe Garay, David Joseph Munzer, Hua Wang 0006. 258-260 [doi]
- 17.2 A Masterless Fault-Tolerant Hybrid Dickson Converter with 95.3% Peak Efficiency 20V-to-60V Input and 3.3V Output for 48V Multi-Phase Automotive ApplicationsMojtaba Ashourloo, Venkata Raghuram Namburi, Gerard Villar Pique, John Pigott, Henk Jan Bergveld, Alaa El Sherif, Olivier Trescases. 258-260 [doi]
- 17.3 A 1.25GHz Fully Integrated DC-DC Converter Using Electromagnetically Coupled Class-D LC OscillatorsAlessandro Novello, Gabriele Atzeni, Giorgio Cristiano, Mathieu Coustans, Taekwang Jang. 260-262 [doi]
- Peak-Current-Controlled Ganged Integrated High-Frequency Buck Voltage Regulators in 22nm CMOS for Robust Cross-Tile Current SharingNachiket V. Desai, Harish K. Krishnamurthy, Khondker Zakir Ahmed, Sheldon Weng, Suhwan Kim, Xiaosen Liu, Huong Do, Kaladhar Radhakrishnan, Krishnan Ravichandran, James W. Tschanz, Vivek De. 262-264 [doi]
- 17.5 A 98.2%-Efficiency Reciprocal Direct Charge Recycling Inductor-First DC-DC ConverterAbdullah Abdulslam, Patrick P. Mercier. 264-266 [doi]
- 17.6 A Reconfigurable DC-DC Converter for Maximum TEG Energy Harvesting in a Battery-Powered Wireless Sensor NodeYoung-Seok Noh, Jeong-Il Seo, Won-Jong Choi, Ji-Hwan Kim, Hoang Van Phuoc, Hyun-Sik Kim, Sang-Gug Lee. 266-268 [doi]
- 17.7 A 0.03mV/mA Low Crosstalk and 185nA Ultra-Low-Quiescent Single-Inductor Multiple-Output Converter Assisted by 5-Input Operational Amplifier for 94.3% Peak Efficiency and 3.0W Driving CapabilityTzu-Hsien Yang, Yong-Hwa Wen, Yu-Jheng Ou Yang, Chun-Kai Chiu, Bo-Kuan Wu, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai. 267-269 [doi]
- 17.8 A 90.5%-Efficiency 28.7µ VRMS-Noise Bipolar-Output High-Step-Up SC DC-DC Converter with Energy-Recycled Regulation and Post-Filtering for ±15V TFT-Based LAE SensorsMin-Woo Ko, Hyun-Ki Han, Hyun-Sik Kim. 270-272 [doi]
- A High-Conversion-Ratio and 97.4% Peak-Efficiency 3-Switch Boost Converter with Duty-Dependent Charge Topology for 1.2A High Driving Current and 20% Reduction of Inductor DC Current in MiniLED ApplicationsYen-An Lin, Si-Yi Li, Zheng-Lun Huang, Chong-Sin Huang, Chin-Hsiang Liang, Kai-Syun Chang, Kai-Cheng Chung, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai. 272-274 [doi]
- Session 18 Overview: Biomedical Devices, Circuits, and Systems Technology Directions SubcommitteeRabia Tugce Yazicigil, Milin Zhang, Patrick P. Mercier. 274-275 [doi]
- 18.1 An Optically-Addressed Nanowire-Based Retinal Prosthesis with 73% RF-to-Stimulation Power Efficiency and 20nC-to-3μ C Wireless Charge TelemeteringAbraham Akinin, Jeremy M. Ford, Jiajia Wu, Chul Kim, Hiren D. Thacker, Patrick P. Mercier, Gert Cauwenberghs. 276-278 [doi]
- CMOS-Driven Pneumatic-Free Scalable Microfluidics and Fluid Processing with Label-Free Cellular and Bio-Molecular Sensing Capability for an End-to-End Point-of-Care SystemChengjie Zhu, Jesus Maldonado, Hao Tang, Suresh Venkatesh, Kaushik Sengupta. 278-280 [doi]
- An Integrated Thermal Actuation/Sensing Array with Stacked Oscillators for Efficient and Localized Heating of Magnetic Nanoparticles with Sub-Millimeter Spatial ResolutionYingYing Fan, Linlin Zhang, Qingbo Zhang, Gang Bao, Taiyun Chi. 280-282 [doi]
- A Wireless Multimodality System-on-a-Chip with Time-Based Resolution Scaling Technique for Chronic Wound MonitoringShao-Yung Lu, Siang-Sin Shan, Shih-Che Kuo, Cheng-Ze Shao, Yung-Hua Yeh, I-Te Lin, Shu-Ping Lin, Yu-Te Liao. 282-284 [doi]
- Session 19 Overview: Optical Systems for Emerging Applications Technology Directions SubcommitteeMunehiko Nagatani, Nick Van Helleputte, Naveen Verma. 284-285 [doi]
- 19.1 Optical Phased-Array FMCW LiDAR with On-Chip CalibrationSungwon Chung, Makoto Nakai, Samer B. Idres, Yongwei Ni, Hossein Hashemi 0001. 286-288 [doi]
- 2 FoVSajjad Moazeni, Eric H. Pollmann, Vivek Boominathan, Filipe A. Cardoso, Jacob T. Robinson, Ashok Veeraraghavan, Kenneth L. Shepard. 288-290 [doi]
- 19.3 A MEMS-Based Dynamic Light Focusing System for Single-Cell Precision in optogeneticsCem Yalcin, Nathan Tessema Ersumo, George Bocchetti, Mohammad Meraj Ghanbari, Nick Antipa, Sina Faraji Alamouti, Laura Waller, Daniel Lopez, Rikky Muller. 290-292 [doi]
- Session 20 Overview: High-Performance VCOs Rf SubcommitteeAndrea Bevilacqua, Salvatore Levantino, Hua Wang. 292-293 [doi]
- 3 PN Corner Without Harmonic TuningHao Guo, Yong Chen 0005, Pui-In Mak, Rui Paulo Martins. 294-296 [doi]
- 20.2 A 3.09-to-4.04GHz Distributed-Boosting and Harmonic-Impedance-Expanding Multi-Core Oscillator with-138.9dBc/Hz at 1MHz Offset and 195.1dBc/Hz FoMYiyang Shu, Huizhen Jenny Qian, Xiang Gao, Xun Luo. 296-298 [doi]
- A 60GHz 186.5dBc/Hz FoM Quad-Core Fundamental VCO Using Circular Triple-Coupled Transformer with No Mode Ambiguity in 65nm CMOSHaikun Jia, Wei Deng 0001, Pingda Guan, Zhihua Wang 0001, Baoyong Chi. 298-300 [doi]
- Session 21 Overview: UWB Systems and Wake-Up Receivers Wireless SubcommitteeHiroyuki Ito, Renaldi Winoto, Yao-Hong Liu. 300-301 [doi]
- 21.1 A 1.125Gb/s 28mW 2m-Radio-Range IR-UWB CMOS TransceiverGeunhaeng Lee, Sanghwa Lee, Ji-Hoon Kim, Tae-Wook Kim. 302-304 [doi]
- 21.2 A 3-to-10GHz 180pJ/b IEEE802.15.4z/4a IR-UWB Coherent Polar Transmitter in 28nm CMOS with Asynchronous Amplitude Pulse-Shaping and Injection-Locked Phase ModulationErwin Allebes, Gaurav Singh, Yuming He, Evgenii Tiurin, Paul Mateman, Ming Ding 0003, Johan Dijkhuis, Gert-Jan van Schaik, Elbert Bechthum, Johan H. C. van den Heuvel, Mohieddine El Soussi, Arjan Breeschoten, Hannu Korpela, Yao-Hong Liu, Christian Bachmann. 304-306 [doi]
- A Fully Integrated 2.7µW -70.2dBm-Sensitivity Wake-Up Receiver with Charge-Domain Analog Front-End, -16.5dB-SIR, FEC and Cryptographic ChecksumKuo-Ken Huang, Jonathan K. Brown, Nicholas Collins, Richard K. Sawyer, Farah B. Yahya, Alice Wang, Nathan E. Roberts, Benton H. Calhoun, David D. Wentzloff. 306-308 [doi]
- 21.4 A 0.75-to-1GHz Passive Wideband Noise-Cancelling 171µW Wake-Up RX and 440µW Primary RX FE with -86dBm/10kb/s Sensitivity, 35dB SIR and 3.8dB RX NFHayden Bialek, Sohail Ahasan, Ali Binaie, Kamala Raghavan Sadagopan, Matthew L. Johnston, Harish Krishnaswamy, Arun Natarajan. 308-310 [doi]
- 21.5 An Integrated 2.4GHz -91.5dBm-Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver Achieving 2μ W at 100ms LatencyHenry L. Bishop, Anjana Dissanayake, Steven M. Bowers, Benton H. Calhoun. 310-312 [doi]
- Session 22 Overview: Terahertz for Communication and Sensing Wireless SubcommitteeQ. Jane Gu, Byung-Wook Min, Maryam Tabesh. 312-313 [doi]
- 22.1 THz Prism: One-Shot Simultaneous Multi-Node Angular Localization Using Spectrum-to-Space Mapping with 360-to-400GHz Broadband Transceiver and Dual-Port Integrated Leaky-Wave AntennasHooman Saeidi, Suresh Venkatesh, Xuyang Lu, Kaushik Sengupta. 314-316 [doi]
- 22.2 A 300GHz-Band Phased-Array Transceiver Using Bi-Directional Outphasing and Hartley Architecture in 65nm CMOSIbrahim Abdo, Carrel da Gomez, Chun Wang, Kota Hatano, Qi Li, Chenxin Liu, Kiyoshi Yanagisawa, Ashbir Aviat Fadila, Jian Pang, Hiroshi Hamada, Hideyuki Nosaka, Atsushi Shirane, Kenichi Okada. 316-318 [doi]
- 22.3 A 0.42THz Coherent TX-RX System Achieving 10dBm EIRP and 27dB NF in 40nm CMOS for Phase-Contrast ImagingDragan Simic, Kaizhe Guo, Patrick Reynaert. 318-320 [doi]
- A 250GHz Autodyne FMCW Radar in 55nm BiCMOS with Micrometer Range ResolutionS. M. Hossein Naghavi, Saghar Seyedabbaszadehesfahlani, Farzad Khoeini, Andreia Cathelin, Ehsan Afshari. 320-322 [doi]
- Session 23 Overview: THz Circuits and Front-Ends Rf SubcommitteeSwaminathan Sankaran, Patrick Reynaert, Shuhei Amakawa. 322-323 [doi]
- 270-to-300GHz Double-Balanced Parametric Upconverter Using Asymmetric MOS Varactors and a Power-Splitting- Transformer Hybrid in 65nm CMOSZhiYu Chen, Wooyeol Choi 0001, K. O. Kenneth. 324-326 [doi]
- 23.2 A 436-to-467GHz Lens-Integrated Reconfigurable Radiating Source with Continuous 2D Steering and Multi-Beam Operations in 65nm CMOSHossein Jalili, Omeed Momeni. 326-328 [doi]
- 23.3 A 605GHz 0.84mW Harmonic Injection-Locked Receiver Achieving 2.3pW/√Hz NEP in 28nm CMOSAriane De Vroede, Patrick Reynaert. 328-330 [doi]
- An 82fsrms-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier- Based Phase Detector in 65nm CMOSSeyeon Yoo, Suneui Park, Seojin Choi, Yoonseo Cho, Heein Yoon, Chanwoong Hwang, Jaehyouk Choi. 330-332 [doi]
- Session 24 Overview: Advanced Embedded Memories Memory SubcommitteeEric Karl, Shinichiro Shiratake, Jonathan Chang. 332-333 [doi]
- 24.1 A 6.2 GHz Single Ended Current Sense Amplifier (CSA) Based Compileable 8T SRAM in 7nm FinFET TechnologyAlexander Fritsch, Rajiv V. Joshi, Sudipto Chakraborty, Holger Wetter, Uma Srinivasan, Matthew Hyde, Otto A. Torreiter, Michael Kugel, Dan Radko, Hyong Kim, Daniel Friedman. 334-336 [doi]
- 2 Cell Size Using Self-Adaptive Delayed Termination and Multi-Cell ReferenceJianguo Yang, Xiaoyong Xue, Xiaoxin Xu, Qiao Wang, Haijun Jiang, Jie Yu, Danian Dong, Feng Zhang 0014, Hangbing Lv, Ming Liu 0022. 336-338 [doi]
- 24.3 A 3nm Gate-All-Around SRAM Featuring an Adaptive Dual-BL and an Adaptive Cell-Power Assist CircuitTaejoong Song, Woojin Rim, Hoonki Kim, Keun Hwi Cho, Taeyeong Kim, Taejung Lee, Geumjong Bae, Dong-Won Kim, S. D. Kwon, Sanghoon Baek, Jonghoon Jung, Jongwook Kye, Hakchul Jung, HyungTae Kim, Soon-Moon Jung, Jaehong Park. 338-340 [doi]
- A 5nm 5.7GHz@1.0V and 1.3GHz@0.5V 4kb Standard-Cell- Based Two-Port Register File with a 16T Bitcell with No Half-Selection IssueHidehiro Fujiwara, Yi-Hsin Nien, Chih-Yu Lin, Hsien-Yu Pan, Hao-Wen Hsu, Shin-Rung Wu, Yao-Yi Liu, Yen-Huei Chen, Hung-Jen Liao, Jonathan Chang. 340-342 [doi]
- Session 25 Overview: DRAM Memory SubcommitteeDong Uk Lee, Bor-Doou Rong, Kyu-hyoun Kim. 342-343 [doi]
- A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise OperationKyunghoon Kim, Joo-Hyung Chae, Jaehyeok Yang, Jihyo Kang, Gang-Sik Lee, Sang-Yeon Byeon, Youngtaek Kim, Boram Kim, Dong-hyun Kim, Yeongmuk Cho, Kangmoo Choi, Hyeongyeol Park, Junghwan Ji, Sera Jeong, Yongsuk Joo, Jaehoon Cha, Minsoo Park, Hongdeuk Kim, Sijun Park, Kyubong Kong, Sunho Kim, Sangkwon Lee, Junhyun Chun, Hyungsoo Kim, Seon-Yong Cha. 344-346 [doi]
- rd-Generation 10nm DRAMYong Hun Kim, Hyung Jin Kim, Jaemin Choi, Min-Su Ahn, Dongkeon Lee, Seung Hyun Cho, Dong-Yeon Park, Young Jae Park, Min-Soo Jang, Yong-Jun Kim, Jinyong Choi, Sung-Woo Yoon, Jae-Woo Jung, Jae-Koo Park, Jae-Woo Lee, Dae Hyun Kwon, Hyung-Seok Cha, Si-Hyeong Cho, Seong-Hoon Kim, Jihwa You, Kyoung-Ho Kim, Dae-Hyun Kim, Byung-Cheol Kim, Young Kwan Kim, Jun-Ho Kim, Seouk-Kyu Choi, Chan Young Kim, Byongwook Na, Hye-In Choi, Reum Oh, Jeong-Don Ihm, Seung-Jun Bae, Nam Sung Kim, Jung-Bae Lee. 346-348 [doi]
- 25.3 An 8Gb GDDR6X DRAM Achieving 22Gb/s/pin with Single-Ended PAM4 SignalingTimothy M. Hollis, Ronny Schneider, Martin Brox, Thomas Hein, Wolfgang Spirkl, Martin Bach, Mani Balakrishnan, Stefan Dietrich, Fabien Funfrock, Milena Ivanov, Natalija Jovanovic, Maksim Kuzmenka, Daniel Lauber, Juan Ocon Garrido, David Ovard, Karl Pfefferl, Sven Piatkowski, Gabriele Piscopo, Manfred Plan, Jens Polney, Jan Pottgiesser, Stephan Rau, Filippo Vitale, Marc Walter, Marcos Alvarez Gonzalez, Martin Broschwitz, Cristian Chetreanu, Andrea Sorrentino, Jörg Weller, Peter Mayer, Michael Richter 0003, Casto Salobrena Garcia, Andreas Schneider, Shih Nern Wong. 348-350 [doi]
- 25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning ApplicationsYoung-Cheon Kwon, Suk-Han Lee, Jaehoon Lee, Sang-Hyuk Kwon, Je-Min Ryu, Jong-Pil Son, Seongil O, Hak-soo Yu, Haesuk Lee, Soo Young Kim, Youngmin Cho, Jin Guk Kim, Jongyoon Choi, Hyunsung Shin, Jin Kim, BengSeng Phuah, HyoungMin Kim, Myeong Jun Song, Ahn Choi, Daeho Kim, Sooyoung Kim, Eun-Bong Kim, David Wang, Shinhaeng Kang, Yuhwan Ro, Seungwoo Seo, Joon Ho Song, Jaeyoun Youn, Kyomin Sohn, Nam Sung Kim. 350-352 [doi]
- Session 26 Overview: RF Power-Amplifier and Front-End Techniques Rf SubcommitteeHongtao Xu, Toshiya Mitomo, James F. Buckwalter. 352-353 [doi]
- A 26-to-60GHz Continuous Coupler-Doherty Linear Power Amplifier for Over-An-Octave Back-Off Efficiency EnhancementTzu-Yuan Huang, Mannem Naga Sasikanth, Sensen Li, Doohwan Jung, Min-Yu Huang, Hua Wang 0006. 354-356 [doi]
- 26.2 A Doherty-Like Load-Modulated Balanced Power Amplifier Achieving 15.5dBm Average Pout and 20% Average PAE at a Data Rate of 18Gb/s in 28nm CMOSValdrin Qunaj, Patrick Reynaert. 356-358 [doi]
- 26.4 A Reflection-Coefficient Sensor for 28GHz Beamforming Transmitters in 22nm FD-SOI CMOSYang Zhang, Giovanni Mangraviti, Johan Nguyen, Zhiwei Zong, Piet Wambacq. 360-362 [doi]
- 26.5 A Watt-Level Quadrature Switched/Floated-Capacitor Power Amplifier with Back-Off Efficiency Enhancement in Complex Domain Using Reconfigurable Self-Coupling Canceling TransformerBingzheng Yang, Huizhen Jenny Qian, Xun Luo. 362-364 [doi]
- 26.6 A 5-to-6GHz Current-Mode Subharmonic Switching Digital Power Amplifier for Enhancing Power Back-Off EfficiencyAoyang Zhang, Ce Yang, Mostafa Ayesh, Mike Shuo-Wei Chen. 364-366 [doi]
- An Impedance-Transforming N-Path Filter Offering Passive Voltage GainMohammad Khorshidian, Harish Krishnaswamy. 365-367 [doi]
- Session 27 Overview: Discrete-Time ADCs Data Converters SubcommitteeJohn Keane, Chih-Cheng Hsieh, Bob Verbruggen. 368-369 [doi]
- th-Order Noise-Shaping SAR Using Capacitor Stacking and Dynamic BufferingJiaxin Liu, Dengquan Li, Yi Zhong, Xiyuan Tang, Nan Sun. 369-371 [doi]
- 14.1-ENOB 184.9dB-FoM Capacitor-Array-Assisted Cascaded Charge-Injection SAR ADCKyojin Choo, Hyochan An, Dennis Sylvester, David T. Blaauw. 372-374 [doi]
- rd-Order Noise-Shaping SAR in a Single-Amplifier EF-CIFF Structure with Fully Dynamic Hardware-Reusing kT/C Noise CancelationTzu-Han Wang, Ruowei Wu, Vasu Gupta, Shaolan Li. 374-376 [doi]
- A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter AmplifierXiyuan Tang, Xiangxing Yang, Jiaxin Liu, Wei Shi, David Z. Pan, Nan Sun. 376-378 [doi]
- An 80MHz-BW 640MS/s Time-Interleaved Passive Noise- Shaping SAR ADC in 22nm FDSOI ProcessChin-Yu Lin, Ying-Zu Lin, Chih-Hou Tsai, Chao-Hsin Lu. 378-380 [doi]
- 27.6 A 25MHz-BW 75dB-SNDR Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Background Offset CalibrationHongshuai Zhang, Yan Zhu 0001, Chi-Hang Chan, Rui Paulo Martins. 380-382 [doi]
- A 79dB-SNDR 167dB-FoM Bandpass ΔΣ ADC Combining N-Path Filter with Noise-Shaping SARLinxiao Shen, Zijie Gao, Xiangxing Yang, Wei Shi, Nan Sun. 382-384 [doi]
- Session 28 Overview: Biomedical Systems Imagers, Medical, Mems and Displays SubcommitteeJoonsung Bae, Jennifer Lloyd, Chris Van Hoof. 384-385 [doi]
- A Distortion-Free VCO-Based Sensor-to-Digital Front-End Achieving 178.9dB FoM and 128dB SFDR with a Calibration-Free Differential Pulse-Code Modulation TechniqueJiannan Huang, Patrick P. Mercier. 386-388 [doi]
- A 400-to-1000nm 24μ W Monolithic PPG Sensor with 0.3A/W Spectral Responsivity for Miniature WearablesSung-Jin Jung, Jeil Ryu, Wanghyun Kim, Seunghoon Lee, Jongboo Kim, Hyelim Park, Taeyoul Jang, Haedo Jeong, Juhwa Kim, Jeongho Park, Raeyoung Kim, Jeonghoon Park, HeeJae Jo, Whee Jin Kim, Jangbeom Yang, Bongjin Sohn, Yuncheol Han, Inchun Lim, Seoungjae Yoo, Changsoon Park, Dae-Geun Jang, Byung-Hoon Ko, Jeongwook Lim, Jihon Kim, Kyungho Lee, Jesuk Lee, Yongin Park, Long Yan. 388-390 [doi]
- A 28μW 134dB DR 2nd-Order Noise-Shaping Slope Light-to-Digital Converter for Chest PPG MonitoringQiuyang Lin, Shuang Song 0003, Roland Van Wegberg, Mario Konijnenburg, Dwaipayan Biswas, Chris Van Hoof, Filip Tavernier, Nick Van Helleputte. 390-392 [doi]
- nd-Order VCO-Based ExG-to-Digital Front-End Using a Multiphase Gated-Inverted Ring-Oscillator QuantizerCorentin Pochet, Jiannan Huang, Patrick P. Mercier, Drew A. Hall. 392-394 [doi]
- 28.5 A 0.6V/0.9V 26.6-to-119.3µW ΔΣ-Based Bio-Impedance Readout IC with 101.9dB SNR and <0.1Hz 1/f CornerTanTan Zhang, Hyunwoo Son, Yuan Gao 0011, Jingjing Lan, Chun-Huat Heng. 394-396 [doi]
- 28.6 A 22.6µ W Biopotential Amplifier with Adaptive Common-Mode Interference Cancelation Achieving Total-CMRR of 104dB and CMI Tolerance of 15Vpp in 0.18µm CMOSNahmil Koo, Hyojun Kim, SeongHwan Cho. 396-398 [doi]
- 2 Scalable Neural Recording Front-End for Fully Immersible Neural Probes Based on a Two-Step Incremental Delta-Sigma Converter with Extended Counting and Hardware ReuseDaniel Wendler, Daniel De Dorigo, Mohammad Amayreh, Alexander Bleitner, Maximilian Marx 0002, Yiannos Manoli. 398-400 [doi]
- nd-Order Opamp-Less ΔΣ ADCsMaged ElAnsary, Jianxiong Xu, José B. Sales Filho, Gairik Dutta, Liam Long, Aly Shoukry, Camilo Tejeiro, Chenxi Tang, Enver Kilinc, Jaimin Joshi, Parisa Sabetian, Samantha Unger, José Zariffa, Paul B. Yoo, Roman Genov. 400-402 [doi]
- Session 29 Overview: Digital Circuits for Computing, Clocking and Power Management DIGITAL CIRCUITS SUBCOMMITTEEPing-Hsuan Hsieh, Mingoo Seok, Keith A. Bowman. 402-403 [doi]
- 29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write VerificationJong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury. 404-406 [doi]
- A 21×21 Dynamic-Precision Bit-Serial Computing Graph Accelerator for Solving Partial Differential Equations Using Finite Difference MethodJunjie Mu, Bongjin Kim. 406-408 [doi]
- 29.3 80ns Fast-Lock 0.4-to-6.5GHz Clock Generator with Self- Referenced Asynchronous Adaptive Droop MitigationPraveen Mosalikanti, Qi Wang, Kuan-Yueh James Shen, Mark Neidengard, Syed Feruz Syed Farooq, Vaughn Grossnickle, Nasser A. Kurd. 408-410 [doi]
- 29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional SpurQiaochu Zhang, Shiyu Su, Cheng-Ru Ho, Mike Shuo-Wei Chen. 410-412 [doi]
- 2 1.5mW 0.625-to-200MHz Fractional Output Divider with 120fsrms Jitter Based on Replica-DTC-Free Background CalibrationChun-Yu Lin, Yu-Ting Hung, Tun-Ju Wang, Tsung-Hsien Lin. 412-414 [doi]
- 29.6 A Distributed Digital LDO with Time-Multiplexing Calibration Loop Achieving 40A/mm2 Current Density and 1mA-to-6.4A Ultra-Wide Load Range in 5nm FinFET CMOSDong-Hoon Jung, Tae-Hwang Kong, Jun Hyeok Yang, Sangho Kim, Kwangho Kim, Jeongpyo Park, Michael Choi, Jongshin Shin. 414-416 [doi]
- A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOSChi-Hsiang Huang 0001, Xun Sun, Yidong Chen, Rajesh Pamula 0001, Arindam Mandal, Visvesh Sathe 0001. 416-418 [doi]
- Session 30 Overview: Non-Volatile Memories Memory SubcommitteeYasuhiko Taito, Violante Moschiano, Shinichiro Shiratake. 420-421 [doi]
- 2 Density with a Peripheral Circuit Under Cell Array ArchitectureJae-Woo Park, Doogon Kim, Sunghwa Ok, Jaebeom Park, Taeheui Kwon, Hyunsoo Lee, Sungmook Lim, Sun-Young Jung, Hyeong-Jin Choi, Taikyu Kang, Gwan Park, Chul-Woo Yang, Jeong-Gil Choi, Gwihan Ko, Jae-Hyeon Shin, Ingon Yang, Junghoon Nam, Hyeokchan Sohn, Seok-in Hong, Yohan Jeong, Sung-Wook Choi, Changwoon Choi, Hyun-Soo Shin, Junyoun Lim, Dongkyu Youn, Sanghyuk Nam, Juyeab Lee, Myungkyu Ahn, Hoseok Lee, Seungpil Lee, Jongmin Park, Kichang Gwon, Woopyo Jeong, Jungdal Choi, Jinkook Kim, Kyowon Jin. 422-423 [doi]
- 2 Bit DensityAli Khakifirooz, Sriram Balasubrahmanyam, Richard Fastow, Kristopher H. Gaewsky, Chang-Wan Ha, Rezaul Haque, Owen Jungroth, Steven Law, Aliasgar S. Madraswala, Binh Ngo, Naveen Prabhu V, Shantanu Rajwade, Karthikeyan Ramamurthi, Rohit S. Shenoy, Jacqueline Snyder, Cindy Sun, Deepak Thimmegowda, Bharat Pathak, Pranav Kalavade. 424-426 [doi]
- th -Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s InterfaceJiho Cho, D. Chris Kang, Jongyeol Park, Sangwan Nam, Jung-Ho Song, Bong-Kil Jung, Jaedoeg Lyu, Hogil Lee, Won-Tae Kim, Hongsoo Jeon, Sunghoon Kim, In-Mo Kim, Jae-Ick Son, Kyoungtae Kang, Sang-Won Shim, Jongchul Park, Eungsuk Lee, Kyung-Min Kang, Sang-Won Park, Jaeyun Lee, Seung-Hyun Moon, Pansuk Kwak, Byunghoon Jeong, Cheon An Lee, Kisung Kim, Junyoung Ko, Tae-Hong Kwon, Junha Lee, Yohan Lee, Chaehoon Kim, Myeong-Woo Lee, Jeong-Yun Yun, Hojun Lee, Yonghyuk Choi, Sanggi Hong, Jonghoon Park, Yoonsung Shin, Hojoon Kim, Hansol Kim, Chiweon Yoon, Dae-Seok Byeon, Seungjae Lee, Jin-yub Lee, Jaihyuk Song. 426-428 [doi]
- 30.4 A 1Tb 3b/Cell 3D-Flash Memory in a 170+ Word-Line-Layer TechnologyTsutomu Higuchi, Takuyo Kodama, Koji Kato, Ryo Fukuda, Naoya Tokiwa, Mitsuhiro Abe, Teruo Takagiwa, Yuki Shimizu, Junji Musha, Katsuaki Sakurai, Jumpei Sato, Tetsuaki Utsumi, Kazuhide Yoneya, Yasuhiro Suematsu, Toshifumi Hashimoto, Takeshi Hioka, Kosuke Yanagidaira, Masatsugu Kojima, Junya Matsuno, Kei Shiraishi, Kensuke Yamamoto, Shintaro Hayashi, Tomoharu Hashiguchi, Kazuko Inuzuka, Akio Sugahara, Mitsuaki Honma, Keiji Tsunoda, Kazumasa Yamamoto, Takahiro Sugimoto, Tomofumi Fujimura, Mizuki Kaneko, Hiroki Date, Osamu Kobayashi, Takatoshi Minamoto, Ryoichi Tachibana, Itaru Yamaguchi, Juan Lee, Venky Ramachandra, Srinivas Rajendra, Tianyu Tang, Siddhesh Darne, Jiwang Lee, Jason Li 0001, Toru Miwa, Ryuji Yamashita, Hiroshi Sugawara, Naoki Ookuma, Masahiro Kano, Hiroyuki Mizukoshi, Yuki Kuniyoshi, Mitsuyuki Watanabe, Kei Akiyama, Hirotoshi Mori, Akira Arimizu, Yoshito Katano, Masakazu Ehama, Hiroshi Maejima, Koji Hosono, Masahiro Yoshihara. 428-430 [doi]
- Session 31 Overview: Analog Techniques Analog SubcommitteeMarco Berkhout, Drew A. Hall, Jiawei Xu. 430-431 [doi]
- 31.1 An 82mW ΔΣ - Based Filter-Less Class-D Headphone Amplifier with -93dB THD+N, 113dB SNR and 93% EfficiencyAtsushi Matamura, Naoaki Nishimura, Preston Birdsong, Abhishek Bandyopadhyay, Adam Spirer, Mariana Markova, Shaolong Liu. 432-434 [doi]
- 31.2 A 0.9V 28MHz Dual-RC Frequency Reference with 5pJ/Cycle and ±200 ppm Inaccuracy from -40°C to 85°CWoojun Choi, Jan A. Angevare, Injun Park, Kofi A. A. Makinwa, Youngcheol Chae. 434-436 [doi]
- 12.1 A 148nW General-Purpose Event-Driven Intelligent Wake-Up Chip for AIoT Devices Using Asynchronous Spike-Based Feature Extractor and Convolutional Neural NetworkZhixuan Wang, Le Ye, Ying Liu, Peng Zhou, Zhichao Tan, Haitao Fan, Yihan Zhang, Jiayoon Ru, Yangyuan Wang, Ru Huang. 436-438 [doi]
- 2 16MHz CMOS RC Frequency Reference with a 1-Point Trimmed Inaccuracy of ±400ppm from -45°C to 85°CHui Jiang, Sining Pan, Çagri Gürleyük, Kofi A. A. Makinwa. 436-438 [doi]
- 31.4 A Chopper-Stabilized Amplifier with -107dB IMD and 28dB Suppression of Chopper-Induced IMDThije Rooijers, Shoubhik Karmakar, Yoshinori Kusuda, Johan H. Huijsing, Kofi A. A. Makinwa. 438-440 [doi]
- Session 32 Overview: Frequency Synthesizers Rf SubcommitteeWei Deng, Jaehyouk Choi, Wanghua Wu. 440-441 [doi]
- A 365fsrms-Jitter and -63dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second/Third- Order Nonlinearity Cancelation and a Probability-Density-Shaping Δ ΣMHangi Park, Chanwoong Hwang, Taeho Seong, Yongsun Lee, Jaehyouk Choi. 442-444 [doi]
- 32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer ChannelsWanghua Wu, Chih-Wei Yao, Chengkai Guo, Pei-Yuan Chiang, Pak-Kim Lau, Lei Chen, Sang-Won Son, Thomas Byunghak Cho. 444-446 [doi]
- A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated JitterMario Mercandelli, Alessio Santiccioli, Simone Mattia Dartizio, Abanob Shehata, Francesco Tesolin, Saleh Karman, Luca Bertulessi, Francesco Buccoleri, Luca Avallone, Angelo Parisi, Andrea Leonardo Lacaita, Michael Peter Kennedy, Carlo Samori, Salvatore Levantino. 445-447 [doi]
- 32.4 A 104fsrms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation TechniqueJuyeop Kim, Yongwoo Jo, Younghyun Lim, Taeho Seong, Hangi Park, Seyeon Yoo, Yongsun Lee, Seojin Choi, Jaehyouk Choi. 448-450 [doi]
- 32.5 A 24GHz Self-Calibrated ADPLL-Based FMCW Synthesizer with 0.01% rms Frequency Error Under 3.2GHz Chirp Bandwidth and 320MHz/μs SlopeZhengkun Shen, Haoyun Jiang, Fan Yang 0077, Yixiao Wang, Zherui Zhang, Junhua Liu, Huailin Liao. 450-452 [doi]
- A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOSEdwin Thaller, Run Levinger, Evgeny Shumaker, Aryeh Farber, Sergey Bershansky, Nir Geron, Ashoke Ravi, Rotem Banin, Jasmin Kadry, Gil Horovitz, Christian Krassnitzer, Christoph Duller, Patrick Torta, Mark Elzinga, Kamran Azadet. 451-453 [doi]
- 32.7 A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop BandwidthJunjun Qiu, Zheng Sun, Bangan Liu, Wenqian Wang, Dingxin Xu, Hans Herdian, Hongye Huang, Yuncheng Zhang, Yun Wang 0008, Atsushi Shirane, Kenichi Okada. 454-456 [doi]
- 32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased ArraysAlessio Santiccioli, Mario Mercandelli, Simone Mattia Dartizio, Francesco Tesolin, Saleh Karman, Abanob Shehata, Luca Bertulessi, Francesco Buccoleri, Luca Avallone, Angelo Parisi, Dmytro Cherniak, Andrea L. Lacaita, Michael Peter Kennedy, Carlo Samori, Salvatore Levantino. 456-458 [doi]
- Session 33 Overview: High-Voltage, GaN and Wireless Power Power Management SubcommitteeMin Chen, Bernhard Wicht, Kousuke Miyaji. 458-459 [doi]
- A Fully Integrated GaN-on-Silicon Gate Driver and GaN Switch with Temperature-compensated Fast Turn-on Technique for Improving ReliabilityHsuan-Yu Chen, Yu-Yung Kao, Zhi Qiang Zhang, Cheng-Hsiang Liao, Hong-Yuan Yang, Ming-Sheng Hsu, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai. 460-462 [doi]
- 33.2 A 600V GaN Active Gate Driver with Dynamic Feedback Delay Compensation Technique Achieving 22.5% Turn-On Energy SavingJing Zhu, Ding Yan, Siyuan Yu, Weifeng Sun, Gang Shi, Siyang Liu, Sen Zhang. 462-464 [doi]
- 33.3 An Automotive-Use 2MHz 100VOUT Flicker-Free Frequency-Modulated GaN-Based Buck-Boost LED Driver Achieving Bootstrap Charge Balancing and 16.8dBμV Radiated EMI Noise ReductionXugang Ke, Wen-Chuen Liu, Min Kyu Song, Jing Xue, Chen Zheng, Kan Liu, Yahui Leng, Min Chen. 464-466 [doi]
- 33.4 An 8A 998A/inch3 90.2% Peak Efficiency 48V-to-1V DC-DC Converter Adopting On-Chip Switch and GaN Hybrid Power ConversionXu Yang, Haixiao Cao, Chenkang Xue, Lenian He, Zhichao Tan, Menglian Zhao, Yong Ding, Wuhua Li, Wanyuan Qu. 466-468 [doi]
- A 1.25W 46.5%-Peak-Efficiency Transformer-in-Package Isolated DC-DC Converter Using Glass-Based Fan-Out Wafer-Level Packaging Achieving 50mW/mm2 Power DensityDongfang Pan, Guolong Li, Fangting Miao, Biao Deng, Junying Wei, Daquan Yu, Ming Liu, Lin Cheng. 468-470 [doi]
- A Wireless Power Transfer System with Up-to-20% Light- Load Efficiency Enhancement and Instant Dynamic Response by Fully Integrated Wireless Hysteretic Control for BioimplantsJunyao Tang, Lei Zhao, Cheng Huang. 470-472 [doi]
- A Frequency-Splitting-Based Wireless Power and Data Transfer IC for Neural Prostheses with Simultaneous 115mWPower and 2.5Mb/s Forward Data DeliveryYechan Park, Seok-Tae Koh, Jeongeun Lee, Hongkyun Kim, Jaesuk Choi, Sohmyung Ha, Chul Kim, Minkyu Je. 472-474 [doi]
- 33.8 A Decentralized Daisy-Chain-Controlled Switched-Capacitor Driver for Microrobotic Actuators with 10× Power-Reduction Factor and Over 300V Drive VoltageYanqiao Li, Benjamin L. Dobbins, Jason T. Stauth. 474-476 [doi]
- 33.9 A Hybrid Switching Supply Modulator Achieving 130MHz Envelope-Tracking Bandwidth and 10W Output Power for 2G/3G/LTE/NR RF Power AmplifiersDongsu Kim, Jun-Suk Bang, Jongbeom Baek, Seungchan Park, Young-Ho Jung, Jae-Yeol Han, Ik-Hwan Kim, Sung-Youb Jung, Takahiro Nomiyama, Ji-Seon Paek, Jongwoo Lee, Thomas Byunghak Cho. 476-478 [doi]
- Session 34 Overview: Emerging Imaging Solutions Imagers, Medical, Mems and Displays SubcommitteeKazuko Nishimura, Johan P. Vanderhaegen, Matteo Perenzoni. 478-479 [doi]
- 34.1 An 8960-Element Ultrasound-on-Chip for Point-of-Care UltrasoundNevada Sanchez, Kailiang Chen, Chao Chen, Dan McMahill, Sewook Hwang, Joseph Lutsky, Jungwook Yang, Liewei Bao, Leung Kin Chiu, Graham Peyton, Hamid Soleimani, Bob Ryan, J. R. Petrus, Youn-Jae Kook, Tyler S. Ralston, Keith Fife, Jonathan Rothberg. 480-482 [doi]
- A 21pJ/frame/pixel Imager and 34pJ/frame/pixel Image Processor for a Low-Vision Augmented-Reality Smart Contact LensRituraj Singh, Stevo Bailey, Phillip Chang, Ashkan Olyaei, Mohammad Hekmat, Renaldi Winoto. 482-484 [doi]
- A 32×32 Pixel 0.46-to-0.75THz Light-Field Camera SoC in 0.13μ m CMOSRitesh Jain, Philipp Hillger, Janusz Grzyb, Eamal Ashna, Vishal Jagtap, Robin Zatta, Ullrich R. Pfeiffer. 484-486 [doi]
- 2 f Dynamic Power ConsumptionJaesuk Choi, Yechan Park, Jung Bum Oh, Jun-Young Kim, Jae Youn Hwang, Sohmyung Ha, Chul Kim, Minkyu Je. 486-488 [doi]
- Session 35 Overview: Adaptive Digital Techniques for Variation Tolerant Systems Digital Circuits SubcommitteeArijit Raychowdhury, Mijung Noh, Keith A. Bowman. 488-489 [doi]
- 35.1 An Octa-Core 2.8/2GHz Dual-Gear Sensor-Assisted High-Speed and Power-Efficient CPU in 7nm FinFET 5G Smartphone SoCBo-Jr Huang, Eric Jia-Wei Fang, Sung S.-Y. Hsueh, Rory Huang, Angus Lin, Chi-hsun Chiang, Yi-Hsuan Lin, Wen-Wen Hsieh, Barry Chen, Yi-Chang Zhuang, Cheng-Yuh Wu, Jia-Ming Chen, Y. S. Chen, Cheng-Tien Wan, Ericbill Wang, Alex Chiou, Ping Kao, Yuwen Tsai, Harry H. Chen, Shih-Arn Hwang. 490-492 [doi]
- 2 PVT-Aware Digital-Flow-Compatible Adaptive Back-Biasing Regulator with Scalable Drivers Achieving 450% Frequency Boosting and 30% Power Reduction in 22nm FDSOI TechnologyYasser Moursy, Thiago Raupp da Rosa, Lionel Jure, Anthony Quelen, Sébastien Genevey, Lionel Pierrefeu, Emmanuel G. Collins Jr., Joerg Winkler, Jonathan Park, Gaël Pillonnet, Vincent Huard, Andrea Bonzo, Philippe Flatresse. 492-494 [doi]
- 35.3 Thread-Level Power Management for a Current- and Temperature-Limiting System in a 7nm Hexagon™ ProcessorVijay Kiran Kalyanam, Eric Mahurin, Keith A. Bowman, Suresh Venkumahanti. 494-496 [doi]
- Session 36 Overview: Hardware Security Digital Architectures and Systems SubcommitteeHirofumi Shinohara, Massimo Alioto, Ingrid Verbauwhede. 496-497 [doi]
- 36.1 Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware SecuritySachin Taneja, Viveka Konandur Rajanna, Massimo Alioto. 498-500 [doi]
- 36.2 An EM/Power SCA-Resilient AES-256 with Synthesizable Signature Attenuation Using Digital-Friendly Current Source and RO-Bleed-Based Integrated Local Feedback and Global Switched-Mode ControlArchisman Ghosh, Debayan Das, Josef Danial, Vivek De, Santosh Ghosh, Shreyas Sen. 499-501 [doi]
- 36.3 A Modeling Attack Resilient Strong PUF with Feedback-SPN Structure Having <0.73% Bit Error Rate Through In-Cell Hot-Carrier Injection Burn-InKunyang Liu, Zihan Fu, Gen Li, Hongliang Pu, Zhibo Guan, Xingyu Wang, Xinpeng Chen, Hirofumi Shinohara. 502-504 [doi]
- A Physically Unclonable Function Combining a Process Mismatch Amplifier in an Oscillator Collapse TopologyJaehan Park, Jae-Yoon Sim. 504-506 [doi]
- 36.5 An Automatic Self-Checking and Healing Physically Unclonable Function (PUF) with <3 × 10⁻⁸ Bit Error RateYan He, Dai Li, Zhanghao Yu, Kaiyuan Yang. 506-508 [doi]
- F1: Striking the Balance Between Energy Efficiency & Flexibility: General-Purpose vs Special-Purpose ML ProcessorsSukHwan Lim, Yongpan Liu, Luca Benini, Tanay Karnik, Hsie-Chia Chang. 513-516 [doi]
- F2: Pushing the Frontiers in Accuracy for Data Converters and Analog CircuitsYoungcheol Chae, Yun-Shiang Shu, Jens Anders, Viola Schaffer, Takashi Oshima, Marco Corsi. 517-519 [doi]
- F3: Silicon Technologies in the Fight Against Pandemics - From Point of Care to Computational EpidemiologyNick Van Helleputte, Arijit Raychowdhury, Ping-Hsuan Hsieh, Jun Deguchi, Matteo Perenzoni, Esther Rodríguez-Villegas, Long Yan, Andreia Cathelin, Keith A. Bowman, Chris Van Hoof. 520-524 [doi]
- F4: Electronics for a Quantum WorldEdoardo Charbon, Alicia Klinefelter, Massimo Alioto, Yao-Hong Liu, Munehiko Nagatani, Arijit Raychowdhury, Andreia Cathelin, Boris Murmann. 525-528 [doi]
- F5: Enabling New System Architectures with 2.5D, 3D, and ChipletsChristopher Gonzalez, Huichu Liu, Mijung Noh, Eric Karl, Thomas Toifl, Shawn Hsu. 529-532 [doi]
- F6: Optical and Electrical Transceivers for 400GbE and BeyondTony Chan Carusone, Sudip Shekhar, Yohan Frans, Wei-Zen Chen, Thomas Toifl, Munehiko Nagatani, Franz Dielacher, William Redman-White. 533-536 [doi]
- SE1: What Technologies Will Shape the Future of Computing?Hugh Mair, Shinichiro Shiratake, Eric Karl, Thomas Burd, Jonathan Chang, Debbie Marr, Samuel Naffziger, Henk Corporaal, Ken Takeuchi, Naresh R. Shanbhag. 537-538 [doi]
- SE2: Going Remote: Challenges and Opportunities to Remote Learning, Work, and CollaborationAlicia Klinefelter, Huichu Liu, Luca Benini, Yvain Thonnart, Keith A. Bowman, Kathy Wilcox, David Bol, Alvin Loke, Ofer Shacham. 539-540 [doi]
- SE3: Favorite Circuit Design and Testing Mistakes of Starting EngineersRamesh Harjani, Mike Chen, Marco Berkhout, Johan H. C. van den Heuvel, Thomas H. Lee, Robert Bogdan Staszewski, Kathleen Philips, Howard C. Luong, Vadim Ivanov. 541-542 [doi]
- SE4: ICs in PandemICsNegar Reiskarimian, Zeynep Toprak Deniz, Ulkuhan Guler, Kathy Wilcox, Alice Wang, Jane Gu, Yaoyao Jia, Alicia Klinefelter, Rikky Muller, Farhana Sheikh, Yildiz Sinangil, Trudy Stetzler, Vivienne Sze, Rabia Tugce Yazicigil, Deeksha Lal, Dina El-Damak. 543-545 [doi]
- SE5: Making a Career ChoiceDenis Daly, Zeynep Lulec, Rabia Tugce Yazicigil, Alison J. Burdett, Rituparna Mandal, Matheus Moreira, Dante G. Muratore, Aisha Walcott-Bryant, Ben Seng-Pan U. 546-547 [doi]
- Special Event: Student Research Preview (SRP)Denis Daly, Jerald Yoo. 548-551 [doi]