Martin Clara - researchr alias

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Viewing Publication 1 - 19 from 19

2021

10.7 A 64GS/s 4×-Interpolated 1b Semi-Digital FIR DAC for Wideband Calibration and BIST of RF-Sampling A/D ConvertersMartin Clara, Daniel Gruber, Albert Molina, Matteo Camponeschi, Yu-Shan Wang, Christian Lindholm, Hundo Shin, Ramon Sanchez, Christoph Duller, Patrick Torta, Kamran Azadet. isscc 2021: 176-178 [doi]

10.6 A 12b 16GS/s RF-Sampling Capacitive DAC for Multi-Band Soft-Radio Base-Station Applications with On-Chip Transmission-Line Matching Network in 16nm FinFETDaniel Gruber, Martin Clara, Ramon Sanchez, Yu-Shan Wang, Christoph Duller, Gerald Rauter, Patrick Torta, Kamran Azadet. isscc 2021: 174-176 [doi]

A 12-b 16-GS/s RF-Sampling Capacitive DAC for Multi-Band Soft Radio Base-Station Applications With On-Chip Transmission-Line Matching Network in 16-nm FinFETDaniel Gruber, Martin Clara, Ramón Sanchez-Perez, Yu-Shan Wang, Christoph Duller, Gerald Rauter, Patrick Torta, Gerhard Knoblinger, Kamran Azadet. jssc, 56(12):3655-3667, 2021. [doi]

2015

A 16-bit 10Gsps current steering RF DAC in 65nm CMOS achieving 65dBc ACLR multi-carrier performance at 4.5GHz FoutGil Engel, Martin Clara, Haiyang Zhu, Paul Wilkins. vlsic 2015: 166 [doi]

2012

A high-input-swing common-mode-robust programmable gain amplifier in 65nm CMOSDaniel Gruber, Martin Clara, Berthold Seger. esscirc 2012: 418-421 [doi]

2011

Jitter Noise of Sampled Multitone SignalsMartin Clara, Nicola Da Dalt. tcas, 58-II(10):652-656, 2011. [doi]

2008

A 1.5V 13bit 130-300MS/s self-calibrated DAC with active output stage and 50MHz signal bandwidth in 0.13μm CMOSMartin Clara, Wolfgang Klatzer, Daniel Gruber, Arnold Marak, Berthold Seger, Wolfgang Pribyl. esscirc 2008: 262-265 [doi]

2007

A 1.5V 200MS/s 13b 25mW DAC with Randomized Nested Background Calibration in 0.13μm CMOSMartin Clara, Wolfgang Klatzer, Berthold Seger, Antonio Di Giandomenico, Luca Gori. isscc 2007: 250-600 [doi]

2006

Clock jitter compensation for current steering DACsAndreas Wiesbauer, Dietmar Straussnigg, Richard Gaggl, Martin Clara, Luis Hernández, Daniel Gruber. iscas 2006: [doi]

2005

A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-/spl mu/m digital CMOSChristoph Sandner, Martin Clara, Andreas Santner, Thomas Hartig, Franz Kuttner. jssc, 40(7):1499-1505, 2005. [doi]

2004

Nonlinear distortion in current-steering D/A-converters due to asymmetrical switching errorsMartin Clara, Andreas Wiesbauer, Wolfgang Klatzer. iscas 2004: 285-288

Low-power 14-bit current steering DAC, for ADSL2+/CO applications in 0.13μm CMOSDario Giotta, Peter Pessl, Martin Clara, Wolfgang Klatzer, Richard Gaggl. esscirc 2004: 163-166 [doi]

Linearity enhancement techniques in low OSR, high clock rate multi-bit continuous-time sigma-delta modulatorsSusana Patón, Thomas Pötscher, Antonio Di Giandomenico, Klaus Kolhaupt, Luis Hernández, Andreas Wiesbauer, Martin Clara, Ramon Frutos. cicc 2004: 527-530 [doi]

A 70-mW 300-MHz CMOS continuous-time /spl Sigma//spl Delta/ ADC with 15-MHz bandwidth and 11 bits of resolutionSusana Patón, Antonio Di Giandomenico, Luis Hernández 0003, Andreas Wiesbauer, Thomas Pötscher, Martin Clara. jssc, 39(7):1056-1063, 2004. [doi]

A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13?m Digital CMOSChristoph Sandner, Martin Clara, Andreas Santner, Thomas Hartig, Franz Kuttner. date 2004: 223-226 [doi]

A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13?m Digital CMOSChristoph Sandner, Martin Clara, Andreas Santner, Thomas Hartig, Franz Kuttner. date 2004: 223-226 [doi]

A 6bit, 1.2GSps low-power flash-ADC in 0.13μm digital CMOSChristoph Sandner, Martin Clara, Andreas Santner, Thomas Hartig, Franz Kuttner. esscirc 2004: 339-342 [doi]

2002

A 1.8 V fully embedded 10 b 160 MS/s two-step ADC in 0.18 μm CMOSMartin Clara, Andreas Wiesbauer, Franz Kuttner. cicc 2002: 437-440 [doi]

A fully integrated analog front-end macro for cable modem applications in 0.18-/spl mu/m CMOSAndreas Wiesbauer, Martin Clara, Moritz Harteneck, Thomas Pötscher, Berthold Seger, Christoph Sandner, Christian Fleischhacker. jssc, 37(7):866-873, 2002. [doi]

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