Table of Contents

• Reconfigurable logic in SoC systemsJack Greenbaum. 5-8 [doi]
• 1-cycle code decompression circuitry for performance increase of Xtensa-1040-based embedded systemsHaris Lekatsas, Jörg Henkel, Venkata Jakkula. 9-12 [doi]
• A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA and customisable I/OMichele Borgatti, Francesco Lertora, Benoit Forst, Lorenzo Cali. 13-16 [doi]
• Loop-based interconnect modeling and optimization approach for multi-GHz clock network designXuejue Huang, Phillip J. Restle, Thomas J. Bucelot, Yu Cao, Tsu-Jae King 0001. 19-22 [doi]
• A signal integrity-driven buffer insertion technique for post-routing noise and delay optimizationKanad Chakraborty, David E. Long, John P. Fishburn, Kishore Singhal, Lun Ye, Christopher Ortiz. 23-26 [doi]
• ADMS-automatic device model synthesizerLaurent Lemaitre, Colin C. McAndrew, Steve Hamm. 27-30 [doi]
• WATSON: a multi-objective design space exploration tool for analog and RF IC designBart De Smedt, Georges G. E. Gielen. 31-34 [doi]
• Integration and system design trends of ADSL analog front ends and hybrid line interfacesSang-Soo Lee. 37-44 [doi]
• A central office combined ADSL-VDSL line driver solution in .35μm CMOSTim Piessens, Michiel Steyaert. 45-48 [doi]
• A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delayHsiang-Hui Chang, Jyh-Woei Lin, Shen-Iuan Liu. 49-52 [doi]
• An architecture for a programmable mixed-signal deviceMonte Mar, Bert Sullam, Eric Blom. 55-58 [doi]
• Nearest neighbour interconnect architecture in deep submicron FPGAsAjay Roopchansingh, Jonathan Rose. 59-62 [doi]
• PipeRench: A virtualized programmable datapath in 0.18 micron technologyHerman Schmit, David Whelihan, Andrew Tsai, Matthew Moe, Benjamin A. Levine, R. Reed Taylor. 63-66 [doi]
• The architecture of dual-mode FPGA embedded system blocksErnie Lin, Steven J. E. Wilton. 67-70 [doi]
• An FPGA based move generator for the game of chessMarc Boule, Zeljko Zilic. 71-74 [doi]
• A deep sub-micron timing measurement circuit using a single-stage Vernier delay lineAntonio H. Chan, Gordon W. Roberts. 77-80 [doi]
• A burn-in tolerant dynamic circuit techniqueAtila Alvandpour, Ram Krishnamurthy 0001, Shekhar Borkar, A. Rahman, Clair Webb. 81-84 [doi]
• Managing soft errors in ASICsLarry Wissel, Scott Pheasant, Rory Loughran, Chris LeBlanc, Bill Klaasen. 85-88 [doi]
• High voltage tolerant ESD design for analog applications in deep submicron CMOS technologiesChung-Hui Chen, Yean-Kuen Fang, Chien-Chun Tsai, Shen Tu, Mark K. L. Chen, Mi-Chang Chang. 89-92 [doi]
• The embedded SCR NMOS and low capacitance ESD protection deviceJian-Hsing Lee, Yi-Hsun Wu, K. R. Peng, R. Y. Chang, Talee Yu, Tong-Chern Ong. 93-96 [doi]
• A simple 1-transistor capacitor-less memory cell for high performance embedded DRAMsPierre C. Fazan, Serguei Okhonin, Mikhail Nagoga, Jean-Michel Sallese. 99-102 [doi]
• An interpolating sense circuit for molecular memoryYoshio Nishida, Wentai Liu. 103-106 [doi]
• A 16 kb 1T1C FeRAM test chip using current-based reference schemeJoseph Wai Kit Siu, Yadollah Eslami, Ali Sheikholeslami, P. Glenn Gulak, Toru Endo, Shoichiro Kawashima. 107-110 [doi]
• Low-power sequential access memory designJoong-Seok Moon, William C. Athas, Peter A. Beerel, Jeffrey T. Draper. 111-114 [doi]
• A self adaptive programming method with 5 mV accuracy for multi-level storage in FLASHLawrence D. Engh, Albert V. Kordesch, Chun Mai-Liu. 115-118 [doi]
• A ROM compression method for continuous dataByung-Do Yang, Lee-Sup Kim. 119-122 [doi]
• High-performance and low-power challenges for sub-70 nm microprocessor circuitsRam K. Krishnamurthy, Atila Alvandpour, Vivek De, Shekhar Borkar. 125-128 [doi]
• A new reduced clock-swing flip-flop: NAND-type keeper flip-flop (NDKFF)Motoki Tokumasu, Hiroshige Fujii, Masako Ohta, Tsunealu Fuse, Atsushi Kameyama. 129-132 [doi]
• 4 Gbps high-density AC coupled interconnectionStephen E. Mick, John M. Wilson 0002, Paul D. Franzon. 133-140 [doi]
• A low power adaptive filter using dynamic reduced 2's-complement representationZhan Yu, Meng-Lin Yu, Kamran Azadet, Alan N. Willson Jr.. 141-144 [doi]
• A 2.29 Gbits/sec, 56 mW non-pipelined Rijndael AES encryption IC in a 1.8 V, 0.18 μm CMOS technologyHenry Kuo, Ingrid Verbauwhede, Patrick Schaumont. 147-150 [doi]
• Burst mode: a new acceleration mode for 128-bit block ciphersYukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa. 151-154 [doi]
• Single-chip FEC codec LSI using iterative CSOC decoder for 10 Gb/s long-haul optical transmission systemsKatsutoshi Seki, Kousuke Mikami, M. Baba, A. Katayama, H. Tanaka, Y. Hara, M. Kobayashi, N. Okada. 155-158 [doi]
• A vector DSP for imagingJohn Redford, Bret Bersack, Matt Monk, Fred Huettig, Dawn Fitzgerald. 159-161 [doi]
• A single-chip MPEG-2 codec based on customizable media microprocessorShunichi Ishiwata, Tomoo Yamakage, Yoshiro Tsuboi, Takayoshi Shimazawa, Tomoko Kitazawa, Shuji Michinaka, Kunihiko Yahagi, Hideki Takeda, Akihiro Oue, Tomoya Kodama, Nobu Matsumoto, Takayuki Kamei, Takashi Miyamori, Goichi Ootomo, Masataka Matsui. 163-166 [doi]
• An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithmMasayuki Miyama, Osamu Tooyama, N. Takamatsu, T. Kodake, K. Nakamura, A. Kato, Junichi Miyakoshi, K. Hashimoto, Shigenobu Komatsu, M. Yagi, Masao Morimoto, Kazuo Taki, Masahiko Yoshimoto. 167-170 [doi]
• A low-power highly-integrated MPEG1/2 audio layer 3 (MP3) decoder for CD-based systemsHenri Cloetens, Reinhard Hahn, Bridget Hooser, Frank Lenke. 171-174 [doi]
• Digital techniques for improved ΔΣ data conversionJose Silva, Xuesheng Wang, Peter Kiss, Un-Ku Moon, Gabor C. Temes. 183-190 [doi]
• A multi-bit sigma-delta ADC for multi-mode receiversMatthew R. Miller, Craig S. Petrie. 191-194 [doi]
• Sub-sampling sigma-delta modulator for baseband processingSrinivasaraman Chandrasekaran, William C. Black Jr.. 195-198 [doi]
• MOSFET modeling for low noise, RF circuit designM. Jamal Deen, Chih Hung Chen, Yuhua Cheng. 201-208 [doi]
• Modeling the gate-related high-frequency and noise characteristics of deep-submicron MOSFETsRainer Kraus, Gerhard Knoblinger. 209-212 [doi]
• Virtual damping in oscillatorsDonhee Ham, Ali Hajimiri. 213-216 [doi]
• Frequency-independent equivalent circuit model for on-chip spiral inductorsYu Cao 0001, Robert A. Groves, Noah Zamdmer, Jean-Olivier Plouchart, Richard A. Wachnik, Xuejue Huang, Tsu-Jae King 0001, Chenming Hu. 217-220 [doi]
• Modeling and optimization of inductors with patterned ground shields for a high performance fully integrated switched tuning VCOFrancis M. Rotella, Jeffrey Zachan. 221-224 [doi]
• Dual mixer downconversion architecture using complex mixing signals: enabling solutions for software defined radiosTajinder Manku, Christopher Snyder, Michele Ting, Yang Ling, Javad Khajehpour, Bill Kung, Lawrence Wong. 227-234 [doi]
• A quadrature direct digital downconverterPeter J. Vancorenland, Philippe Coppejans, Wouter De Cock, Michiel Steyaert. 235-238 [doi]
• A direct conversion receiver for the 3G WCDMA standardRanjit Gharpurey, Naveen Yanduru, Francesco Dantoni, Petteri Litmanen, Guglielmo Sirna, Terry Mayhugh Jr., Charles Lin, Irene Yuanying Deng, Paul Fontaine, Fang Lin. 239-242 [doi]
• Analysis and optimization of IIP2 in CMOS direct down-convertersDanilo Manstretta, Francesco Svelto. 243-246 [doi]
• A monolithic CMOS low-IF Bluetooth receiverWenjun Sheng, Bo Xia, Ahmed Emira, Chunyu Xin, Sung Tae Moon, Ari Yakov Valero-López, Edgar Sánchez-Sinencio. 247-250 [doi]
• A self-calibration technique for mismatches in image-reject receiversMostafa A. I. Elmala, Sherif H. K. Embabi. 251-254 [doi]
• A 402-output TFT-LCD driver IC with power-controlling function by selecting number of colorsTetsuro Itakura, Hironori Minamizaki, Tetsuya Saito, Tadashi Kuroda. 257-260 [doi]
• A 500-dpi cellular-logic processing array for fingerprint-image enhancement and verificationKoji Fujii, Mamoru Nakanishi, Satoshi Shigematsu, Hiroki Morimura, Takahiro Hatano, Namiko Ikeda, Toshishige Shimamura, Yukio Okazaki, Hakaru Kyuragi. 261-264 [doi]
• High dynamic range CMOS image sensor with conditional resetSung-Hyun Yang, Kyoung-Rok Cho. 265-268 [doi]
• SOI Hall effect sensor operating up to 270°CLionel Portmann, Hussein Ballan, Michel J. Declercq. 269-272 [doi]
• On-chip RF spiral inductors and bandpass filters using active magnetic energy recoveryYi-Cheng Wu, M. Frank Chang. 275-278 [doi]
• A 0.18μm CMOS, high Q-enhanced bandpass filter with direct digital tuningChris DeVries, Ralph Mason. 279-282 [doi]
• A 2.1GHz 1.3V 5mW programmable Q-enhancement LC bandpass biquad in 0.35μm CMOSFikret Duelgel, Edgar Sánchez-Sinencio, Jose Silva-Martinez. 283-286 [doi]
• A 2GHz quadrature hybrid implemented in CMOS technologyRobert C. Frye, Sharad Kapur, Robert C. Melville. 287-290 [doi]
• A design methodology for low EMI-noise microprocessor with accurate estimation-reduction-verificationHiroyulu Tsujikawa, Kenji Shimazaki, Shozo Hirano, Motohiro Ohki, Talcashi Yoneda, Hiroshi Benno. 299-302 [doi]
• Design integration, DFT, and verification methodology for an MPEG 1/2 audio layer 3 (MP3) SoC deviceBernhard Birkl, Bridget Hooser, Marc Janssens, Frank Lenke, Vlado Vorisek. 303-306 [doi]
• A design methodology for integrating IP into SOC systemsPhilippe Coussy, Adel Baganne, Eric Martin 0001. 307-310 [doi]
• A voice processing and control module for cable telephony applicationsJoseph T. Nabicht, Jeanne K. Pitz, Patrick P. Siniscalchi, Christopher L. Betty, Stephen Maggiotto, Donald Richardson, Stewart M. DeSoto, Sucheendran Sridharan, Sudheer Vemulapalli, Kenneth Downs, D. George Gata, Ali K. Dweik, David Guidry, Kyle D. Muskoff, Brandon Beckham, Glenn H. Westphal. 311-314 [doi]
• NECoBus: a high-end SOC bus with a portable and low-latency wrapper-based interface mechanismKenichiro Anjo, Atsushi Okamura, Tomoharu Kajiwarat, Noriko Mizushima, Masafumi Omori, Yasuaki Kuroda. 315-318 [doi]
• System-on-chip (SoC) requires IC and package co-design and co-verificationAnna Fontanelli, Stefano Arrigoni, Davide Raccagni, Massimo Rosin. 319-322 [doi]
• Active-feedback frequency compensation for low-power multi-stage amplifiersHoi Lee, Philip K. T. Mok. 325-328 [doi]
• Nested feed-forward Gm-stage and ing resistor plus nested-Miller compensation for multistage amplifiersXiaohong Peng, Willy Sansen. 329-332 [doi]
• Three stage amplifier with positive feedback compensation schemeJoão Ramos, Michiel Steyaert. 333-336 [doi]
• A high gain CMOS operational amplifier with negative conductance gain enhancementJie Yan, Randall L. Geiger. 337-340 [doi]
• A noninvasive channel-select filter for a CMOS Bluetooth receiverAlireza Zolfaghari, Behzad Razavi. 341-344 [doi]
• An AI-calibrated IF filter: a yield enhancement method with area and power dissipation reductionsMasahiro Murakawa, Toshio Adachi, Yoshihiro Nino, Eiichi Takahashi, Yuji Kasai, Kaoru Takasuka, Tetsuya Higuchi. 345-348 [doi]
• A 1.2 Gbps SOI-BiCMOS write driver for hard disk drivesH. Yoshizawa, Yochiro Kobayashi, M. Yoshinaga, Y. Ookuma, K. Maio, K. Irikura. 349-352 [doi]
• A 10Gbase Ethernet transceiver (LAN PHY) in a 1.8 V, 0.18 μm SOI/CMOS technologyTsutomu Yoshimura, Kimio Ueda, Jun Takasoh, Yoshiki Wada, Toshihide Oka, Harufusa Kondoh, Osamu Chiba, Yoshihumi Azekawa, Masahiko Ishiwaki. 355-358 [doi]
• A 2.5 Gbps CMOS optical receiver analog front-endWei-Zen Chen, Chao-Hsin Lu. 359-362 [doi]
• An adaptive PAM-4 5 Gb/s backplane transceiver in 0.25 μm CMOSJeff L. Sonntag, John T. Stonick, James Gorecki, Bill Beale, Bill Check, Xue-Mei Gong, Joe Guiliano, Kyong Lee, Bob Lefferts, David A. Yokoyama-Martin, Un-Ku Moon, Amber Sengir, Stephen Titus, Gu-Yeon Wei, Daniel Weinlader, YaoHua Yang. 363-366 [doi]
• The role of monolithic transmission lines in high-speed integrated circuitsBehzad Razavi. 367-374 [doi]
• Single reference continuous rate clock and data recovery from 30 Mbit/s to 3.2 Gbit/sJan-Peter Frambach, Roeland Heijna, Rob Krosschell. 375-378 [doi]
• Integrated circuits for 3GPP mobile wireless systemsChris Nicol, Matthew Cooke. 381-388 [doi]
• A 80 Mb/s low-power scalable turbo codec coreAlexandre Giulietti, Bruno Bougard, Veerle Derudder, Steven Dupont, Jan-Willem Weijers, Liesbet Van der Perre. 389-392 [doi]
• 600 MHz DSP for baseband processing in 3G base stationsTod Wolf, Dale E. Hocevar, Alan Gatherer, Patrick Geremia, Armelle Laine. 393-396 [doi]
• A low-power W-CDMA demodulator using specially-designed micro-DSPsHiroyuki Igura, Masaru Hirata, Junya Yamada, Masakazu Yamashina, Shigeru Ono. 397-400 [doi]
• Piece-wise parabolic interpolation for direct digital frequency synthesisAhmed M. Eltawil, Babak Daneshrad. 401-404 [doi]
• FLEXBAR: A crossbar switching fabric with improved performance and utilizationJacob Chang, Srivaths Ravi 0001, Anand Raghunathan. 405-408 [doi]
• ESD protection design for RF integrated circuits: new challengesAlbert Z. Wang, Haigang Feng, Rouying Zhan, Guang Chen, Q. Wu. 411-418 [doi]
• A 1 V 0.9 dB NF low noise amplifier for 5-6 GHz WLAN in 0.18 μm CMOSDavid Cassan, John R. Long. 419-422 [doi]
• A low-voltage multi-GHz VCO with 58% tuning range in SOI CMOSNeric H. W. Fong, Jean-Olivier Plouchart, Noah Zamdmer, Duixian Liu, Lawrence F. Wagner, Calvin Plett, Gerry Tarr. 423-426 [doi]
• A 1.8 GHz CMOS fractional-N frequency synthesizer with randomized multi-phase VCOChun-Huat Heng, Bang-Sup Song. 427-430 [doi]
• A 2 MHz GFSK IQ receiver for Bluetooth with DC-tolerant bit slicerBang-Sup Song, Thomas Cho, David Kang, Scott Dow. 431-434 [doi]
• A 1.8 V fully embedded 10 b 160 MS/s two-step ADC in 0.18 μm CMOSMartin Clara, Andreas Wiesbauer, Franz Kuttner. 437-440 [doi]
• A 2.5 V 10 b 120 MSample/s CMOS pipelined ADC with high SFDRSang-Min Yoo, Tae-Hwan Oh, Jung-Woong Moon, Seung-Hoon Lee, Un-Ku Moon. 441-444 [doi]
• A 8-bit 200 MS/s interpolating/averaging CMOS A/D converterJan Vandenbussche, Koen Uyttenhove, Erik Lauwers, Michel S. J. Steyaert, Georges G. E. Gielen. 445-448 [doi]
• Understanding MOSFET mismatch for analog designPatrick G. Drennan, Colin C. McAndrew. 449-452 [doi]
• Spatial averaging and ordering in matched element arraysKannan Krishna, William Bright, D. B. Dye, Khurram Muhammad, Yin Hu. 453-456 [doi]
• A 2-V 23-μA 5.3-ppm/°C 4th-order curvature-compensated CMOS bandgap referenceKa Nang Leung, Philip K. T. Mok, Chi Yat Leung. 457-460 [doi]
• Low-voltage pipelined ADC using opamp-reset switching techniqueDong-Young Chang, Lei Wu, Un-Ku Moon. 461-464 [doi]
• Technology trends and challenges for CMOS/system LSIs for the next 10-15 yearsSeiichiro Kawamura. 467-474 [doi]
• Application-dependent scaling tradeoffs and optimization in the SoC eraCarlos H. Diaz, Mi-Chang Chang, Tong-Chern Ong, Jack Yuan-Chen Sun. 475-478 [doi]
• Modularized low temperature LNO/PZT/LNO ferroelectric capacitor-over-interconnect (COI) FeRAM for advanced SOC (ASOC) applicationS. L. Lung, Dennis Lin, S. S. Chen, Gary Weng, C. L. Liu, S. C. Lai, C.-W. Tsai, T. B. Wu, Rich Liu. 479-482 [doi]
• High speed, low power, optoelectronic InP-based HBT integrated circuitsMarko Sokolich. 483-490 [doi]
• Sea of leads (SoL) characterization and design for compatibility with board-level optical waveguide interconnectionMuhannad S. Bakir, Hollie A. Reed, Anthony V. Mule, Paul A. Kohl, Kevin P. Martin, James D. Meindl. 491-494 [doi]
• A comprehensive geometry-dependent macromodel for substrate noise coupling in heavily doped CMOS processesDicle Ozis, Terri S. Fiez, Kartikeya Mayaram. 497-500 [doi]
• Modeling substrate noise generation in CMOS digital integrated circuitsMakoto Nagata, Takashi Morie, Atsushi Iwata. 501-504 [doi]
• The effect of supply and substrate noise on jitter in ring oscillatorsNathen Barton, Dicle Ozis, Terri S. Fiez, Kartikeya Mayaram. 505-508 [doi]
• Passive closed-form time-domain macromodels for on-chip distributed RC interconnectsAnestis Dounavis, Ramachandra Achar, Michel S. Nakhla. 509-512 [doi]
• Delay and power model for current-mode signaling in deep submicron global interconnectsRizwan Bashirullah, Wentai Liu, Ralph K. Cavin III. 513-516 [doi]
• A comprehensive study of energy dissipation in lossy transmission lines driven by CMOS invertersPayam Heydari, Soroush Abbaspour, Massoud Pedram. 517-520 [doi]
• Measurement results of on-chip IR-dropKazutoshi Kobayashi, Junji Yamaguchi, Hidetoshi Onodera. 521-524 [doi]