Hsiang-Hui Chang - researchr alias

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Viewing Publication 1 - 15 from 15

2013

2011

2009

A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration SchemesPing-Ying Wang, Jing-Hong Conan Zhan, Hsiang-Hui Chang, Hsiu-Ming (Sherman) Chang. jssc, 44(8):2182-2192, 2009. [doi]

2008

2006

A 0.7-2-GHz self-calibrated multiphase delay-locked loopHsiang-Hui Chang, Jung-Yu Chang, Chun-Yi Kuo, Shen-Iuan Liu. jssc, 41(5):1051-1061, 2006. [doi]

2005

A wide-range and fast-locking all-digital cycle-controlled delay-locked loopHsiang-Hui Chang, Shen-Iuan Liu. jssc, 40(3):661-670, 2005. [doi]

2004

Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnectionHsiang-Hui Chang, Rong-Jyi Yang, Shen-Iuan Liu. tcas, 51-I(12):2356-2364, 2004. [doi]

2003

A fast locking and low jitter delay-locked loop using DHDLHsiang-Hui Chang, Jyh-Woei Lin, Shen-Iuan Liu. jssc, 38(2):343-346, 2003. [doi]

A spread-spectrum clock generator with triangular modulationHsiang-Hui Chang, I-Hui Hua, Shen-Iuan Liu. jssc, 38(4):673-676, 2003. [doi]

A shifted-averaging VCO with precise multiphase outputs and low jitter operationHsiang-Hui Chang, Shang-Ping Chen, Shen-Iuan Liu. esscirc 2003: 647-650 [doi]

2002

A wide-range delay-locked loop with a fixed latency of one clock cycleHsiang-Hui Chang, Jyh-Woei Lin, Ching-Yuan Yang, Shen-Iuan Liu. jssc, 37(8):1021-1027, 2002. [doi]

A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delayHsiang-Hui Chang, Jyh-Woei Lin, Shen-Iuan Liu. cicc 2002: 49-52 [doi]

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