Table of Contents

• Complex signal processing is not - complexKenneth Martin. 3-14 [doi]
• Taking a system approach to energy managementDennis M. Monticelli. 15-19 [doi]
• RF-trends in mobile communicationJosef Fenk. 21-27 [doi]
• Transistor operation and circuit performance in organic electronicsEugenio Cantatore, E. J. Meijer. 29-36 [doi]
• Emerging non-volatile memory technologiesGerhard Muller, Nicolas Nagel, Cay-Uwe Pinnow, Thomas Roehr. 37-44 [doi]
• IP related activities in Toshiba and Japanese SoC industriesTakashi Yoshimori. 45-48 [doi]
• A scaleable instruction buffer for a configurable DSP coreChristian Panis, Michael Bramberger, Herbert Grünbacher, Jari Nurmi. 49-52 [doi]
• A low power 3D rendering engine with two texture units and 29Mb embedded DRAM for 3G multimedia terminalsRamchan Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun Song, Hoi-Jun Yoo. 53-56 [doi]
• An area-efficient standard-cell floating-point unit design for a processing-in-memory systemJoong-Seok Moon, Taek-Jun Kwon, Jeff Sondeen, Jeffrey Draper. 57-60 [doi]
• A 1000FPS@128×128 vision processor with 8-bit digitized I/OGustavo Liñán Cembrano, Ángel Rodríguez-Vázquez, Rafael Castro-López, Servando Espejo-Meana. 61-64 [doi]
• An analog image processing LSI employing scanning line-parallel processingTeruyasu Taguchi, Makoto Ogawa, Tadashi Shibata. 65-68 [doi]
• Micropower mixed-signal acoustic localizerMilutin Stanacevic, Gert Cauwenberghs. 69-72 [doi]
• A 50 GHz direct injection locked oscillator topology as low power frequency divider in 0.13 μm CMOSMarc Tiebout. 73-76 [doi]
• A 15 GHz 256/257 dual-modulus prescaler in 120 nm CMOSHans-Dieter Wohlmuth, Daniel Kehrer. 77-80 [doi]
• A digitally tuned 1.1 GHz subharmonic injection-locked VCO in 0.18μm CMOSHesham Ahmed, Christopher A. DeVries, Ralph Mason. 81-84 [doi]
• A digital quadrature modulator with on-chip D/A converterJohan Sommarek, Jouko Vankka, Jaakko Ketola, Ilari Teikari, Kari Halonen. 85-88 [doi]
• 2Kevin O'Sullivan, Chris Gorman, Michael Hennessy, Vincent Callaghan. 89-92 [doi]
• Single-side-band digital-to-analog converters for Nyquist signal generationJurgen Deveugele, Pieter Palmers, Michiel Steyaert. 93-96 [doi]
• A Σ-Δ fractional-N frequency synthesizer using a wideband integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applicationsHan-Il Lee, Je-Kwang Cho, Kun-Seok Lee, In-Chul Hwang, Tae-Won Ahn, Kyung-suc Nah, Byeong-ha Park. 97-100 [doi]
• A compact, low-power low-jitter digital PLLAmr M. Fahim. 101-104 [doi]
• A low voltage, 10-2550MHz, 0.15μ CMOS, process and divider modulus independent PLL using zero-VT MOSFETsAdrian Maxim. 105-108 [doi]
• A 1-V 13-mW 2.5-GHz double-rate phase-locked loop with phase alignment for zero delayGerry C. T. Leung, Howard C. Luong. 109-112 [doi]
• A 1-V 5.2-GHz 27.5-mW fully-integrated CMOS WLAN synthesizerGerry C. T. Leung, Howard C. Luong. 113-116 [doi]
• A CMOS photodiode array with in-pixel data acquisition systemRoger Steadman, Armin Kemna, Francisco Morales Serrano, Gereon Vogtmeier, Erol Özkan 0001, Werner Brockherde, Bedrich J. Hosticka. 117-120 [doi]
• CMOS x-ray image sensor with pixel level A/D conversionJose G. Rocha, N. F. Ramos, Reinoud F. Wolffenbuttel, José Higino Correia. 121-124 [doi]
• A smart image sensor with high-speed feeble ID-beacon detection for augmented reality systemYusuke Oike, Makoto Ikeda, Kunihiro Asada. 125-128 [doi]
• A CMOS focal-plane rotation sensor with retinal processing circuitKuan-Hsun Huang, Li-Ju Lin, Chung-Yu Wu. 129-132 [doi]
• A readout circuit for QWIP infrared detector arrays using current mirroring integrationMurat Tepegoz, Tayfun Akin. 133-136 [doi]
• Linearization of monolithic LNAs using low-frequency low-impedance input terminationVladimir Aparin, Lawrence E. Larson. 137-140 [doi]
• A 1.8-V wide-band CMOS LNA for multiband multistandard front-end receiverAdiseno, Håkan Magnusson, Håkan K. Olsson. 141-144 [doi]
• Design of high gain fully-integrated distributed amplifiers in 0.35 μm CMOSRony E. Amaya, Calvin Plett. 145-148 [doi]
• 17GHz and 24GHz LNA designs based on extended-S-parameter with microstrip-on-die in 0.18μm logic CMOS technologyLuiz M. Franca-Neto, Bradley A. Bloechel, Krishnamurthy Soumyanath. 149-152 [doi]
• Inductor-less, 10Gb/s limiter with 10mV sensitivity and offset/temperature compensation in baseline CMOS18Mihai A. T. Sanduleanu, Eduard Stikvoort. 153-156 [doi]
• A fully-integrated two-channel A/D interface for the acquisition of cardiac signals in implantable pacemakersAndrea Gerosa, Andrea Maniero, Andrea Neviani. 157-160 [doi]
• A 16-bit 60μW multi-bit ΣΔ modulator for portable ECG applicationsJonny Johansson, Harald Neubauer, Hans Hauer. 161-164 [doi]
• A micro power continuous-time ΣΔ modulatorLourans Samid, Yiannos Manoli. 165-168 [doi]
• A very area/power efficient mixed signal circuit for voice signal processing in 0.18 digital technologyJoão Risques, Jorge Duarte, Vasco Amaro, Seng-Pan U, Kuok Vai Chiang, Ka-Fai Chang, Keng Chong Lai. 169-172 [doi]
• A low-power entropy-coding analog/digital converter with integrated data compressionR. Peck, Dietmar Schroeder. 173-176 [doi]
• Energy minimization method for optimal energy-delay extractionHoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija. 177-180 [doi]
• A time borrowing selectively clocked skewed logic for high-performance circuits in scaled technologiesNaran Sirisantana, Kaushik Roy 0001. 181-184 [doi]
• High performance pipelining method for static circuits using heterogeneous pipelining elementsManish Garg. 185-188 [doi]
• A high-speed logic circuit family with interdigitated array structure for deep sub-micron IC designHiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada. 189-192 [doi]
• An 8-channel, 12-bit, 20 MHz fully differential tester IC for analog and mixed-signal circuitsMohamed M. Hafed, Gordon W. Roberts. 193-196 [doi]
• A serial 10 gigabit Ethernet transceiver on digital 0.13μm CMOSBin Wu, Yue-Hong Sutu, Karthik Ramamurthy, Dong Zheng, Eugene Cheung, Toan Tran, Yong Jiang, Manoj Rana. 197-200 [doi]
• A DSP-based digital IF AM/FM car-radio receiverFrancesco Adduci, Marzia Annovazzi, Gianluigi Boarin, A. Colaci, Vittorio Colonna, Gabriele Gandolfi, Michele Sala, Fabrizio Salidu, Fabrizio Stefani, Martin Frey, P. Kirchlechner, Christian Kutschenreiter, Andrea Baschirotto. 201-204 [doi]
• Custom silicon implementation of a delayless acoustic echo canceller algorithmAnders Berkeman, Viktor Öwall. 205-208 [doi]
• A novel universal battery charger for NiCd, NiMH, Li-ion and Li-polymerFloriberto A. Lima, J. N. Ramalho, D. Tavares, J. Duarte, C. Albuquerque, T. Marques, A. Geraldes, A. P. Casimiro, Gert Renkema, J. Been, Wouter Groeneveld. 209-212 [doi]
• A contactless smartcard designed with asynchronous circuit techniquePui-Lam Siu, Chiu-sing Choy, Chi Fat Chan, Kong-Pang Pun. 213-216 [doi]
• A quad-band low power single chip direct conversion CMOS transceiver with ΣΔ-modulation loop for GSMEdmund Götz, Hans Krobel, Gunter Marzinger, Bernd Memmler, Christian Muenker, Burkhard Neurauter, Dirk Romer, Jorn Rubach, Werner Schelmbauer, Markus Scholz, Martin Simon, Ulrich Steinacker, Claus Stoger. 217-220 [doi]
• A single-chip, 5.15GHz-5.35GHz, 2.4GHz-2.5GHz, 0.18μm CMOS RF transceiver for 802.11a/b/g wireless LANKostis Vavelidis, Iason Vassiliou, Theodore Georgantas, Akira Yamanaka, Spyros Kavadias, George Kamoulakos, Charalampos Kapnistis, Yiannis Kokolakis, Aris Kyranas, Panagiotis Merakos, Ilias Bouras, Stamatis Bouras, Sofoklis Plevridis, Nikos Haralabidis. 221-224 [doi]
• A dual-mode direct-conversion CMOS transceiver for Bluetooth and 802.11bYeon-Jae Jung, Hoesam Jeong, Eunseok Song, Jungho Lee, Seung Wook Lee, Donghyeon Seo, Inho Song, Sanghun Jung, Joonbae Park, Deog Kyoon Jeong, Wonchan Kim. 225-228 [doi]
• A highly integrated, dual-band, multi-mode wireless LAN transceiverThomas Rühlicke, Markus Zannoth, Bernd-Ulrich Klepser. 229-232 [doi]
• A 15 MHz bandwidth sigma-delta ADC with 11 bits of resolution in 0.13μm CMOSAntonio Di Giandomenico, Susana Patón, Andreas Wiesbauer, Luis Hernández 0003, Thomas Pötscher, Lukas Dörrer. 233-236 [doi]
• A 400-MHz 6-bit ADC with a partial analog equalizer for coaxial cable channelsAmir Hadji-Abdolhamid, David Andrew Johns. 237-240 [doi]
• A 1.8V 100mW 12-bits 80Msample/s two-step ADC in 0.18-μm CMOSAmir Zjajo, Hendrik van der Ploeg, Maarten Vertregt. 241-244 [doi]
• 10-bit, 3 mW continuous-time sigma-delta ADC for UMTS in a 0.12 μm CMOS processLukas Dörrer, Franz Kuttner, Andreas Wiesbauer, Antonio Di Giandomenico, Thomas Hartig. 245-248 [doi]
• A continuous-time sigma-delta modulator with switched capacitor controlled current mode feedbackMaurits Ortmanns, Friedel Gerfers, Yiannos Manoli. 249-252 [doi]
• Modelling impact of digital substrate noise on embedded regenerative comparatorsYann A. Zinzius, Georges G. E. Gielen, Willy Sansen. 253-256 [doi]
• Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrateMustafa Badaroglu, Lakshmanan Balasubramanian, Kris Tiri, Vincent Gravot, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man. 257-260 [doi]
• Aggressor aware repeater circuits for improving on-chip bus performance and robustnessAtul Katoch, Sanjeev K. Jain, Maurice Meijer. 261-264 [doi]
• Clock net optimization using active shieldingHimanshu Kaul, Dennis Sylvester, David T. Blaauw. 265-268 [doi]
• Passive integration and RF MEMS: a toolkit for adaptive LC circuitsTheo G. S. M. Rijks, Joost T. M. van Beek, M. J. E. Ulenaers, Jeroen De Coster, Robert Puers, Arnold den Dekker, L. van Teeffelen. 269-272 [doi]
• Single chip, low supply voltage piezoelectric transformer controllerEnrico Dallago, Alberto Danioni, Giulio Ricotti, Giuseppe Venchi. 273-276 [doi]
• 24 Gb/s laser/modulator driver IC using 0.2μm gate length PHEMTsTing Huang, Zhigong Wang, En Zhu, Xiaoming Wang, Mingzhen Xiong. 277-280 [doi]
• A CMOS 10Gb/s SONET transceiverHarish S. Muthali, Thomas P. Thomas, Ian A. Young. 281-284 [doi]
• 10 Gb/s CMOS limiting amplifier for optical linksRui Tao, Manfred Berroth. 285-287 [doi]
• 10 Gb/s single-ended laser driver in 0.35μm SiGe BiCMOS technologyChia-Ming Tsai, Li-Ren Huang, Day-Uei Li, Chien-fu Chang. 289-292 [doi]
• A CMOS single-ended OTA with high CMRRMaxim Pribytko, Patrick J. Quinn. 293-296 [doi]
• A 0.8-V, 8-μW, CMOS OTA with 50-dB gain and 1.2-MHz GBW in 18-pF loadLibin Yao, Michiel Steyaert, Willy Sansen. 297-300 [doi]
• A 1.8-V 73-dB dynamic-range CMOS variable gain amplifierRyutaro Saito, Kinya Hosoda, Akira Hyogo, Takaya Maruyama, Hiroshi Komuraki, Hisayasu Sato, Keitaro Sekine. 301-304 [doi]
• Optimization of device dimensions for high-performance low-power architecture blocksTobias Gemmeke, Michael Gansen, Thomas G. Noll, Heinrich J. Stockmanns. 305-308 [doi]
• New digital circuit techniques for total standby leakage reduction in nano-scale SOI technologyKoushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown. 309-312 [doi]
• Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologiesRahul M. Rao, Jeffrey L. Burns, Richard B. Brown. 313-316 [doi]
• A gate leakage reduction strategy for future CMOS circuitsMindaugas Drazdziulis, Per Larsson-Edefors. 317-320 [doi]
• Power-performance optimal 64-bit carry-lookahead addersRadu Zlatanovici, Borivoje Nikolic. 321-324 [doi]
• A CMOS receiver for a pulsed time-of-flight laser rangefinderJan Nissinen, Pasi Palojärvi, Juha Kostamovaara. 325-328 [doi]
• A micro-hotplate-based monolithic CMOS thermal analysis systemDiego Barrettino, Wan Ho Song, Markus Graf, Andreas Hierlemann, Henry Baltes. 329-332 [doi]
• A 4×64 pixel CMOS image sensor for 3D measurement applicationsOlaf M. Schrey, O. Elkhalili, Peter Mengel, M. Petermann, Werner Brockherde, Bedrich J. Hosticka. 333-336 [doi]
• DNA electrical detection based on inductor resonance frequency in standard CMOS technologyG. Laurent, Luis Moreno Hagelsieb, Dimitri Lederer, P. E. Lobert, Denis Flandre, J. Remacle, Jean-Pierre Raskin. 337-340 [doi]
• A low-noise 1.8Gbps bipolar OEICRobert Swoboda, Horst Zimmermann. 341-344 [doi]
• A 19-23 GHz integrated LC-VCO in a production 70 GHz fT SiGe technologyHugo Veenstra, Edwin van der Heijden. 349-352 [doi]
• Fully integrated 10 GHz CMOS VCO for multi-band WLAN applicationsLaurent Perraud, Jean-Louis Bonnot, Nicolas Sornin, Christophe Pinatel. 353-356 [doi]
• A 31 GHz CML ring VCO with 5.4 ps delay in a 0.12-μm SOI CMOS technologyJean-Olivier Plouchart, Jonghae Kim, Noah Zamdmer, Melanie Sherony, Yue Tan, Meeyoung Yoon, Mohamed Talbi, Asit Ray, Lawrence F. Wagner. 357-360 [doi]
• 10 GHz quadrature-phase voltage controlled oscillator and prescalerWei-Zen Chen, Chien-Liang Kuo, Chia-Chun Liu. 361-364 [doi]
• Three stage amplifier frequency compensationJoão Ramos, Xiaohong Peng, Michiel Steyaert, Willy Sansen. 365-368 [doi]
• Dynamic biasing: a low power linearisation techniquePhilippe Coppejans, Michiel Steyaert. 369-372 [doi]
• 1.5V rail-to-rail programmable-gain CMOS amplifierJaime Ramírez-Angulo, Antonio J. López-Martín, Ramón González Carvajal, Chad Lackey. 373-376 [doi]
• Input/output rail-to-rail video op-amp with constant behaviour over the entire voltage rangeJuan M. Carrillo, J. Francisco Duque-Carrillo, Guido Torelli, José L. Ausín. 377-380 [doi]
• Opamp with 106 dB DC gain in 120nm digital CMOSFranz Schlögl, Horst Zimmermann. 381-384 [doi]
• A 20 Gb/s 82mW one-stage 4:1 multiplexer in 0.13 μm CMOSDaniel Kehrer, Hans-Dieter Wohlmuth. 385-388 [doi]
• A 3.125-Gb/s CMOS word alignment demultiplexer for serial data communicationsWen Hu Zhao, Zhi-Gong Wang, En Zhu. 389-392 [doi]
• A direct digital frequency synthesis system for low power communicationsAlistair McEwan, Syed Ahmar Shah, Steve Collins. 393-396 [doi]
• Direct digital frequency synthesis with dual-slope approachAntonio Giuseppe Maria Strollo, Davide De Caro, Ettore Napoli, Nicola Petra. 397-400 [doi]
• Bitline leakage equalization for sub-100nm cachesAtila Alvandpour, Dinesh Somasekhar, Ram Krishnamurthy 0001, Vivek De, Shekhar Borkar, Christer Svensson. 401-404 [doi]
• A novel hierarchical multi-port cacheZhaomin Zhu, Koh Johguchi, Hans Jürgen Mattausch, Tetsushi Koide, Tai Hirakawa, Tetsuo Hironaka. 405-408 [doi]
• A yield-optimized latch-type SRAM sense amplifierBernhard Wicht, Thomas Nirschl, Doris Schmitt-Landsiedel. 409-412 [doi]
• Low voltage sensing techniques and secondary design issues for sub-90nm cachesManoj Sinha, Steven Hsu, Atila Alvandpour, Wayne P. Burleson, Ram Krishnamurthy 0001, Shekhar Borkar. 413-416 [doi]
• A 0.6mA, 0.9V 100MHz FM front-end in a 0.18μm CMOS-D technologyThierry Melly, Erwan Le Roux, David Ruffieux, Vincent Peiris. 417-420 [doi]
• A cable-modem RF tunerKari Stadius, Arto Malinen, Petri Järviö, Kari Halonen, Petteri Paatsila. 421-424 [doi]
• A 0.35μ CMOS fractional-N transmitter for 315/433/868/915 MHz ISM applicationsP. Jacobs, Johan Janssens, Tomas Geurts, Jan Crols. 425-428 [doi]
• A fast modulator for dynamic supply linear RF power amplifierNicolas Schlumpf, Michel J. Declercq, Catherine Dehollain. 429-432 [doi]
• A CDMA2000 zero IF receiver with low-leakage integrated front-endHelen Waite, P. Ta, Jennie Chen, H. Li, M. Gao, C. S. Chang, Y. S. Chang, William Redman-White, Olivier Charlon, Y. Fan, R. Perkins, D. Brunel, E. Soudee. 433-436 [doi]
• A 62 dB dynamic range sixth-order band pass filter with 100-175 MHz tuning rangeConcepción Aldea, Santiago Celma, Aránzazu Otín. 437-440 [doi]
• Continuously tunable, very long time constant CMOS integrator for a neural recording implantRobert Rieger, Andreas Demosthenous, John Taylor 0002. 441-444 [doi]
• Programmable switched capacitor 4-tap FIR filterHeikki Repo, Timo Rahkonen. 445-448 [doi]
• A widely tunable CMOS Gm-C filter with a negative source degeneration resistor transconductorShinichi Hori, Tadashi Maeda, Hitoshi Yano, Noriaki Matsuno, Keiichi Numata, Nobuhide Yoshida, Yuji Takahashi, Tomoyuki Yamase, Robert Walkington, Hikaru Hikaru. 449-452 [doi]
• A high-speed and lightweight on-chip crossbar switch scheduler for on-chip interconnection networksKangmin Lee, Se-Joong Lee, Hoi-Jun Yoo. 453-456 [doi]
• A linear high voltage charge pump for MEMs applications in 0.18μm CMOS technologyManuel Innocent, Piet Wambacq, Stéphane Donnay, Willy Sansen, Hugo De Man. 457-460 [doi]
• A 10Gbps/port 8×8 shared bus switch with embedded DRAM hierarchical output bufferKangmin Lee, Se-Joong Lee, Hoi-Jun Yoo. 461-464 [doi]
• Monolithic time-to-digital converter with 20ps resolutionSimone Tisa, A. Lotito, Andrea Carlo Giudice, Franco Zappa. 465-468 [doi]
• A CMOS time-to-digital converter based on a ring oscillator for a laser radarIlkka Nissinen, Antti Mäntyniemi, Juha Kostamovaara. 469-472 [doi]
• Verification of a blind mismatch error equalization method for randomly interleaved ADCs using a 2.5V/12b/30MSs PSAADCMartin Anderson, Jonas Elbornsson, Jan-Erik Eklund, Joakim Alvbrant, Henrik Fredriksson. 473-476 [doi]
• A low power sample-and-hold amplifierHitoshi Tani, Yoshihisa Fujimoto, Masahiko Maruyama, Hiroyuki Akada, Hiroaki Ogawa, Masayuki Miyamoto. 477-480 [doi]
• A simple design methodology for increased ESD robustness of CMOS core cellsAlbert Jan Huitsing, Theo Smedes, H.-U. Schroder. 481-484 [doi]
• A 1mW 40-190MHz BJT logarithmic biquadEmmanuel M. Drakakis. 485-488 [doi]
• A 18GHz rotary traveling wave VCO in CMOS with I/Q outputsGregoìre Le Grand de Mercey. 489-492 [doi]
• On-chip integration of dipole antenna and VCO using standard BiCMOS technology for 10 GHz applicationsFaycal Touati, Michel Pons. 493-496 [doi]
• A low voltage, low power VCO for the 88-108MHz FM broadcasting bandDavid Ruffieux, Erwan Le Roux, Thierry Melly, Vincent Peiris. 497-500 [doi]
• Differentially "bathtub"-tuned CMOS VCO using inductively coupled varactorsSander L. J. Gierkink, Robert C. Frye, Vito Boccuzzi. 501-504 [doi]
• A 2.4GHz SiGe low phase-noise VCO using on chip tapped inductorPing Wing Lai, Laszlo Dobos, Stephen Long. 505-508 [doi]
• A 19.2GOPS, 20mW adaptive FIR filterMiguel E. Figueroa, Seth Bridges, David Hsu, Chris Diorio. 509-512 [doi]
• A 330-MHz 15-b quadrature digital synthesizer/mixer in 0.25-μm CMOSYongchul Song, Beomsup Kim. 513-516 [doi]
• An ADSL integrated active hybrid circuitJames R. Hellums, Richard K. Hester, Marco Corsi, Tobin Hagan, Robert L. Halbach. 517-520 [doi]
• Embedded CMOS distributed voltage regulator for large core loadsFloriberto A. Lima, A. Geraldes, T. Marques, J. N. Ramalho, P. Casimiro. 521-524 [doi]
• Phase frequency detectors for fast frequency acquisition in zero-dead-zone CPPLLs for mobile communication systemsKun-Seok Lee, Byeong-ha Park, Han-Il Lee, Min Jong Yoh. 525-528 [doi]
• Oscillator pulling and synchronisation issues in self-oscillating class D power amplifiersTim Piessens, Michiel Steyaert. 529-532 [doi]
• Integrated overcurrent protection for class D power stagesMarco Berkhout. 533-536 [doi]
• CMOS output drivers with reduced ground bounce and electromagnetic emissionBernd Deutschmann, Timm Ostermann. 537-540 [doi]
• A highly linear fully differential low power CMOS line driverKhayrollah Hadidi, Hiroyuki Oshima, Masahiro Sasaki, Takashi Matsumoto 0001. 541-544 [doi]
• A low-voltage fully-monolithic ΔΣ-based class-D audio amplifierJorge Varona, Anas A. Hamoui, Kenneth W. Martin. 545-548 [doi]
• A 10Gb/s fully differential CMOS transimpedance preamplifierRui Tao, Manfred Berroth. 549-552 [doi]
• Modified CMOS Cherry-Hooper amplifiers with source follower feedback in 0.35μm technologyChris D. Holdenried, Michael W. Lynch, James W. Haslett. 553-556 [doi]
• A 10Gb/s SiGe compact laser diode driver using push-pull emitter followers and miller compensated output switchAdrian Maxim. 557-560 [doi]
• A fully integrated 5.3 GHz, 2.4V, 0.3 W SiGe-bipolar power amplifier with 50Ω outputWinfried Bakalski, Werner Simbürger, Ronald Thüringer, Andriy Vasylyev, Arpad L. Scholtz. 561-564 [doi]
• A 0.75-3.6GHz SiGe direct-conversion quadrature-modulatorEsa Tiiliharju, Kari Halonen. 565-568 [doi]
• Bond pad and ESD protection structure for 0.25μm/0.18μm RF-CMOSDomine Leenaerts, Rudolf Velghe. 569-572 [doi]
• A highly integrated CMOS direct digital RF quadrature modulatorYijun Zhou, Jiren Yuan. 573-576 [doi]
• A 1V fully integrated CMOS transformer based mixer with 5.5dB gain, 14.5dB SSB noise figure and 0dBm input IP3Marc Tiebout, Thomas Liebermann. 577-580 [doi]
• A wide range temperature stable integrated current referenceMatthias Radecker, Alois Knoll, Robert Kocaman, Viktor Buguszewicz, Ralf Rudolf. 583-586 [doi]
• A versatile structure of S31-GGA-casc switched-current memory cell with complex suppression of memorizing errorsOndrej Subrt. 587-590 [doi]
• Analytic model for area and power constrained optimal repeater insertionGiuseppe S. Garcea, Nick van der Meijs, Ralph H. J. M. Otten. 591-594 [doi]
• Continuous representation of the performance of a CMOS libraryB. Lasbouygues, J. Schindler, Sylvain Engels, Philippe Maurine, Nadine Azémard, Daniel Auvergne. 595-598 [doi]
• An ultra low-power adiabatic adder embedded in a standard 0.13μm CMOS environmentEttore Amirante, Jürgen Fischer, Markus Lang, Agnese Bargagli-Stoffi, Jörg Berthold, Christoph Heer, Doris Schmitt-Landsiedel. 599-602 [doi]
• A small-area high performance 512-point 2-dimensional FFT single-chip processorNaoto Miyamoto, Leo Karnan, Kazuyuki Maruo, Koji Kotani, Tadahiro Ohmi. 603-606 [doi]
• Low voltage, high-Q SOI MEMS varactors for RF applicationsArda Deniz Yalcinkaya, Søren Jensen, Ole Hansen. 607-610 [doi]
• Monolithic SOI-MEMS capacitive pressure sensor with standard bulk CMOS readout circuitMiikka Ylimaula, Markku Åberg, Jyrki Kiihamaki, Hannu Ronkainen. 611-614 [doi]
• A block matching approach for movement estimation in a CMOS retina: principle and resultsD. Navarro, Guy Cathébras, F. Gensolen. 615-618 [doi]
• A cycle-accurate joulemeter for CMOS VLSI circuitsEunseok Song, In-Chan Choi, Young-Kil Park, Soo-Ik Chae. 619-622 [doi]
• The sense amplifier common mode effect on a switching current-mode power staged based on sigma-delta modulationEnrico Dallago, Fabio Quaglia, Giuseppe Venchi. 623-626 [doi]
• CMOS transistor mismatch model valid from weak to strong inversionTeresa Serrano-Gotarredona, Bernabé Linares-Barranco. 627-630 [doi]
• Implementation of a bandwidth-efficient M-FSK demodulator for powerline communicationsGerasimos Maniatis, Konstantinos Efstathiou 0002, George Papadopoulos. 631 [doi]
• Minimizing inductive noise in system-on-a-chip with multiple power gating structuresSuhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz, David F. Heidel, Michael Immediato. 635-638 [doi]
• Multiple-bit parallel-CDMA technique for an on-chip interface featuring high data transmission rate, small latency and high noise toleranceShinsaku Shimizu, Toshimasa Matsuoka, Kenji Taniguchi 0001. 639-642 [doi]
• Model and verification of triple-well shielding on substrate noise in mixed-signal CMOS ICsRoberto Rossi, Guido Torelli, Valentino Liberali. 643-646 [doi]
• A shifted-averaging VCO with precise multiphase outputs and low jitter operationHsiang-Hui Chang, Shang-Ping Chen, Shen-Iuan Liu. 647-650 [doi]
• A ΔΣ fractional-N frequency synthesizer with a multi-band PMOS VCOs for 2.4 and 5GHz WLAN applicationsJohn W. M. Rogers, Mark S. Cavin, Fa Foster Dai, David G. Rahn. 651-654 [doi]
• Wideband LNA for a multistandard wireless receiver in 0.18 μm CMOSStefan Andersson, Christer Svenson, Oskar Drugge. 655-658 [doi]
• A 0.9V body effect feedback 2 GHz low noise amplifierThierry Taris, Jean-Baptiste Bégueret, Hervé Lapuyade, Yann Deval. 659-662 [doi]
• A dual-band enhanced harmonic rejection filter for modulators in GSM and DCS transmittersPeng-Un Su, June-Ming Hsu. 663-666 [doi]
• A 3.3 V self-biased 2.4-2.5GHz high linearity PHEMT MMIC power amplifierChen-Kuo Chu, Hou-Kuei Huang, Chih-Cheng Wang, Yeong-Her Wang, Chuang-Chin Hsu, Wang Wu, Chang-Luen Wu, Chian-Sern Chang. 667-670 [doi]
• MOSFET mismatch in weak/moderate inversion: model needs and implications for analog designLaurent Vancaillie, Fernando Silveira, Bernabé Linares-Barranco, Teresa Serrano-Gotarredona, Denis Flandre. 671-674 [doi]
• x commutator for low cost Bluetooth solutionsVincent Knopik, Didier Belot. 675-678 [doi]
• CMOS ring oscillator with quadrature outputs and 100 MHz to 3.5 GHz tuning rangeMarkus Grozing, Bernd Phillip, Manfred Berroth. 679-682 [doi]
• A 9-16Gb/s clock and data recovery circuit with three-state phase detector and dual-path loop architectureAfshin Rezayee, Kenneth Martin. 683-686 [doi]
• A 1V 10-mW monolithic Bluetooth receiver in a 0.35μm CMOS processVincent Sin-Luen Cheung, Howard C. Luong. 687-690 [doi]
• A complementary Colpitts oscillator based on 0.35 μm CMOS technologyChoong-Yul Cha, Sang-Gug Lee 0001. 691-694 [doi]
• A voltage-controlled oscillator for IEEE 802.11a and HiperLAN2 applicationAndrea Giovanni Bonfanti, Salvatore Levantino, Stefano Pellerano, Carlo Samori, Andrea L. Lacaita, F. Torrisi. 695-698 [doi]
• Low power quadrature VCO with the back-gate couplingHye-Ryoung Kim, Seung-Min Oh, Sungdo Kim, Young Sik Youn, Sang-Gug Lee 0001. 699-701 [doi]
• Comparison of distance mismatch and pair matching of CMOS devicesUlrich Schaper, Carsten Linnenbank. 703-705 [doi]
• IF-to-digital converter for FM/AM/IBOC radioQuino Sandifort, Lucien J. Breems, Eise Carel Dijkmans, Han Schuurmans. 707-710 [doi]
• Offset calibrating comparator array for 1.2-V, 6bit, 4-Gsample/s flash ADCs using 0.13μm generic CMOS technologyHiroyuki Okada, Yasuyuki Hashimoto, Kohji Sakata, Toshiro Tsukada, Koichiro Ishibashi. 711-714 [doi]
• An analytical approach to the estimation of dynamic non-linearity parameters in pipeline A/D convertersMohammad Taherzadeh-Sani, Reza Lotfi, Omid Shoaei. 715-718 [doi]
• A 75mW 10bit 120MSample/s parallel pipeline ADCDaisuke Miyazaki, Masanori Furuta, Shoji Kawahito. 719-722 [doi]
• A low power and high speed Viterbi decoder chip for WLAN applicationsChien-Ching Lin, Chia-Cho Wu, Chen-Yi Lee. 723-726 [doi]