Yasuyuki Hashimoto - researchr alias

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Viewing Publication 1 - 5 from 5

2006

Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and BeyondKoichiro Ishibashi, Tetsuya Fujimoto, Takahiro Yamashita, Hiroyuki Okada, Yukio Arima, Yasuyuki Hashimoto, Kohji Sakata, Isao Minematsu, Yasuo Itoh, Haruki Toda, Motoi Ichihashi, Yoshihide Komatsu, Masato Hagiwara, Toshiro Tsukada. ieicet, 89-C(3):250-262, 2006. [doi]

2005

Feedforward-type parasitic capacitance canceler and its application to 4 Gb/s T/H circuitTakahide Sato, Shigetaka Takagi, Nobuo Fujii, Yasuyuki Hashimoto, Kohji Sakata, Hiroyuki Okada. iscas 2005: 5561-5564 [doi]

An on-chip active decoupling circuit to suppress crosstalk in deep-submicron CMOS mixed-signal SoCsToshiro Tsukada, Yasuyuki Hashimoto, Kohji Sakata, Hiroyuki Okada, Koichiro Ishibashi. jssc, 40(1):67-79, 2005. [doi]

2004

4-Gb/s track and hold circuit using parasitic capacitance canceller [flash ADC application]Takahide Sato, Shigetaka Takagi, Nobuo Fujii, Yasuyuki Hashimoto, Kohji Sakata, Hirovuki Okada. esscirc 2004: 347-350 [doi]

2003

Offset calibrating comparator array for 1.2-V, 6bit, 4-Gsample/s flash ADCs using 0.13μm generic CMOS technologyHiroyuki Okada, Yasuyuki Hashimoto, Kohji Sakata, Toshiro Tsukada, Koichiro Ishibashi. esscirc 2003: 711-714 [doi]

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