Table of Contents

• On ambient intelligence, needful things and process technologiesCarel J. van der Poel, Francesco Pessolano, Raf Roovers, Frans Widdershoven, G. de Walle, Emile H. L. Aarts, Phillip Christie. 3-10 [doi]
• Low power digital circuit designTakayasu Sakurai. 11-18 [doi]
• Integrated circuits for the biology-to-silicon interface [biotechnology]Roland Thewes, Christian Paulus, Meinrad Schienle, Franz Hofmann, Alexander Frey, Ralf Brederlow, Petra Schindler-Bauer, Marcin K. Augustyniak, Melanie Atzesberger, Birgit Holzapfl, Martin Jenkner, Björn Eversmann, Gottfried Beer, Michaela Fritz, Thomas Haneder, Hans-Christian Hanke. 19-28 [doi]
• Low voltage and low power aspects of data converter designQiuting Huang. 29-35 [doi]
• Technology considerations for automotiveHerman Casier, Peter Moens, Koen Appeltans. 37-41 [doi]
• UWB considerations for "my personal global adaptive network" (MAGNET) systemsJohn F. M. Gerrits, John R. Farserotu, John R. Long. 45-56 [doi]
• Assessment of the merits of CMOS technology scaling for analog circuit designMaarten Vertregt, Peter C. S. Scholtens. 57-63 [doi]
• DSP: a technology, a product, a revolutionGene A. Frantz. 65-68 [doi]
• A wideband high-linearity RF receiver front-end in CMOSVincent J. Arkesteijn, Eric A. M. Klumperink, Bram Nauta. 71-74 [doi]
• Silicon bipolar up and down-converters for 5-GHz WLAN applicationsEgidio Ragonese, Alessandro Italia, Luca La Paglia, Giuseppe Palmisano. 75-78 [doi]
• An integrated low power CMOS baseband analog design for direct conversion receiverMinkyung Lee, Ickjin Kwon, Kwyro Lee. 79-82 [doi]
• 60 GHz transceiver circuits in SiGe:C BiCMOS technologyWolfgang Winkler, Johannes Borngräber, Hans Gustat, Falk Korndörfer. 83-86 [doi]
• L1/L2 dual-band CMOS GPS receiverJongmoon Kim, Sanghyun Cho, Jinho Ko. 87-90 [doi]
• 2.4-GHz receiver for sensor applicationsJere A. M. Järvinen, Jouni Kaukovuori, Jussi Ryynanen, Jarkko Jussila, Kalle Kivekäs, Kari A. I. Halonen. 91-94 [doi]
• A multi-mode continuously-tunable lowpass filter for zero-IF mobile applicationsDavid Chamla, Andreas Kaiser, Andreia Cathelin, Didier Belot. 95-98 [doi]
• Low-power widely tunable Gm-C filter with an adaptive DC-blocking, triode-biased MOSFET transconductorShinichi Hori, Tadashi Maeda, Noriaki Matsuno, Hikaru Hida. 99-102 [doi]
• m-C baseband filter with automatic frequency tuning for a direct conversion IEEE802.11a wireless LAN receiverBo Shi, Weiyun Shan. 103-106 [doi]
• Temperature stabilised tunable Gm-C filter for very low frequenciesPaolo Bruschi, Giuseppe Barillaro, Francesco Pieri, Massimo Piotto. 107-110 [doi]
• A highly linear pseudo-differential transconductance [CMOS OTA]Faramarz Bahmani, Edgar Sánchez-Sinencio. 111-114 [doi]
• A high-linear 160-MHz CMOS PGA [programmable gain amplifier]Belén Calvo, Santiago Celma, Maria Teresa Sanz. 115-118 [doi]
• Performance degradation of an LC-tank VCO by impact of digital switching noiseCharlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay. 119-122 [doi]
• A technique to reduce flicker noise up-conversion in CMOS LC voltage-controlled oscillatorsHyman Shanan, Michael Peter Kennedy. 123-126 [doi]
• A harmonic quadrature LO generator using a 90° delay-locked loop [zero-IF transceiver applications]Jan Craninckx, Vincent Gravot, Stéphane Donnay. 127-130 [doi]
• LC-oscillators above 100 GHz in silicon-based technologyWolfgang Winkler, Johannes Borngräber, Bernd Heinemann. 131-134 [doi]
• 55GHz CMOS frequency divider with 3.2GHz locking rangeKen Yamamoto, Minoru Fujishima. 135-138 [doi]
• A wideband CMOS VCO for zero-IF GSM-CDMA single-chip transceiverKostas Manetakis, Darryl Jessie, Chiewcharn Narathong. 139-142 [doi]
• Transconductance with capacitances feedback compensation for multistage amplifiersXiaohong Peng, Willy Sansen. 143-146 [doi]
• A 0.5-V bulk-input fully differential operational transconductance amplifierShouri Chatterjee, Yannis P. Tsividis, Peter R. Kinget. 147-150 [doi]
• A 14-V high speed driver in 5-V-only 0.35-μm standard CMOSDirk Killat, Oliver Salzmann, Andreas Baumgaertner. 151-154 [doi]
• 2 7.25mW per-channel audio stereo-DAC with 97dB-DR and 39dB SNRoutVittorio Colonna, Marzia Annovazzi, Gianluigi Boarin, Gabriele Gandolfi, Fabrizio Stefani, Andrea Baschirotto. 155-158 [doi]
• A digital modulator with bandpass delta-sigma modulatorJohan Sommarek, Jouko Vankka, Jaakko Ketola, Jonne Lindeberg, Kari Halonen. 159-162 [doi]
• Low-power 14-bit current steering DAC, for ADSL2+/CO applications in 0.13μm CMOSDario Giotta, Peter Pessl, Martin Clara, Wolfgang Klatzer, Richard Gaggl. 163-166 [doi]
• A 14-bit 130-MHz CMOS current-steering DAC with adjustable INLTao Chen, Peter Geens, Geert Van der Plas, Wim Dehaene, Georges G. E. Gielen. 167-170 [doi]
• A power cut-off technique for gate leakage suppression [CMOS logic circuits]Mindaugas Draidiiulis, Per Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson. 171-174 [doi]
• Efficiency of body biasing in 90 nm CMOS for low power digital circuitsKlaus von Arnim, Eduardo Borinski, Peter Seegebrecht, Horst Fiedler, Ralf Brederlow, Roland Thewes, Jörg Berthold, Christian Pacha. 175-178 [doi]
• Charge recycling sense amplifier based logic: securing low power security ICs against DPA [differential power analysis]Kris Tiri, Ingrid Verbauwhede. 179-182 [doi]
• A 3mW continuous-time ΣΔ-modulator for EDGE/GSM with high adjacent channel toleranceMarkus Schimper, Lukas Dörrer, Ettore Riccio, Georgi Panov. 183-186 [doi]
• A sigma-delta modulator with bitstream-controlled dynamic element matchingMichiel A. P. Pertijs, Johan H. Huijsing. 187-190 [doi]
• A 120dB 300mW stereo audio A/D converter with 110dB THD+NPrasad Ammisetti, Amiya Chokhawala, Karl Thompson, John Melanson. 191-194 [doi]
• A 48-860 MHz TV splitter amplifier exhibiting an IIP2 and IIP3 of 94dBmV and 73dBmVJan van Sinderen, Marc Notten, Eduard Stikvoort, Francois Seneschal. 195-198 [doi]
• A 5.0mW 0dBm FSK transmitter for 315/433 MHz ISM applications in 0.25 μm CMOSNico Boom, Wim Rens, Jan Crols. 199-202 [doi]
• A 5.2-GHz silicon bipolar power amplifier for IEEE 802.11a and HIPERLAN2 wireless LANsAntonino Scuderi, Francesco Carrara, Guiseppe Palmisano. 203-206 [doi]
• 4-Mb MOSFET-selected phase-change memory experimental chipFerdinando Bedeschi, Roberto Bez, Chiara Boffino, Edoardo Bonizzoni, Egidio Cassiodoro Buda, Giulio Casagrande, Lucio Costa, Marco Ferraro, Roberto Gastaldi, Osama Khouri, Federica Ottogalli, Fabio Pellizzer, Agostino Pirovano, Claudio Resta, Guido Torelli, Marina Tosi. 207-210 [doi]
• Variability analysis for sub-100 nm PD/SOI CMOS SRAM cellRajiv V. Joshi, Saibal Mukhopadhyay, Donald W. Plass, Yuen H. Chan, Ching-Te Chuang, Anirudh Devgan. 211-214 [doi]
• A high density, low leakage, 5T SRAM for embedded cachesIngvar Carlson, Stefan Anderson, Sreedhar Natarajan, Atila Alvandpour. 215-218 [doi]
• The impact of random doping effects on CMOS SRAM cellBinjie Cheng, Scott Roy, Asen Asenov. 219-222 [doi]
• A 2.4GHz-bandwidth OEIC with voltage-up-converter [optical receiver]Robert Swoboda, Johannes Knorr, Horst Zimmermann. 223-226 [doi]
• Ultra high-compliance CMOS current mirrors for low voltage charge pumps and referencesOlivier Charlon, William Redman-White. 227-230 [doi]
• Power-efficient super class AB OTAsAntonio Lopez-Martin, Sushmita Baswa, Jaime Ramírez-Angulo, Ramón G. Carvajal. 231-234 [doi]
• CMOS V-I converter with 75dB SFDR and 360μW power consumptionSotir Ouzounov, Engel Roza, Hans Hegt, Gerard Van der Weide, Arthur H. M. van Roermund. 235-238 [doi]
• 1.5 GHz OPAMP in 120nm digital CMOSFranz Schlögl, Horst Zimmermann. 239-242 [doi]
• Thermally optimized demagnetization of inductive loads [power IC load switching]Wolfgang Horn, Peter Singerl. 243-246 [doi]
• A 97mW 110MS/s 12b pipeline ADC implemented in 0.18μm digital CMOSTerje N. Andersen, Atle Briskemyr, Frode Telstø, Johnny Bjørnsen, Thomas E. Bonnerud, Bjørnar Hernes, Øystein Moldsvor. 247-250 [doi]
• 2 low-power A/D-converter cell for 10b 10MS/s operationDavid Muthers, Reinhard Tielert. 251-254 [doi]
• A 2.7mW 1MSps 10b analog-to-digital converter with built-in reference buffer and 1LSB accuracy programmable input rangesPierangelo Confalonieri, Marco Zamprogno, Francesca Girardi, Germano Nicollini, Angelo Nagari. 255-258 [doi]
• A configurable time-interleaved pipeline ADC for multi-standard wireless receiversBo Xia, Alberto Valdes-Garcia, Edgar Sánchez-Sinencio. 259-262 [doi]
• A 1.8 V, 10 Gbps fully integrated CMOS optical receiver analog front endWei-Zen Chen, Ying-Lien Cheng. 263-266 [doi]
• Optical receiver IC for CD/DVD/blue-laser applicationJohannes Sturm, Martin Leifhelm, Harald Schatzmayr, Stefan Groiss, Horst Zimmermann. 267-270 [doi]
• Design of low noise CMOS OEIC for blu-ray disc optical storage systemsMarco Giardina, A. Stek, G. W. de Jong, Jos R. M. Bergervoet. 271-274 [doi]
• Two high-speed optical front-ends with integrated photodiodes in standard 0.18 μm CMOSCarolien Hermans, Paul Leroux, Michiel Steyaert. 275-278 [doi]
• 5 Gbps 0.35-μm CMOS driver for laser diode or optical modulatorLianming Li, Ting Huang, Jun Feng, Zhigong Wang, Mingzhen Xiong. 279-282 [doi]
• Burst-mode transmitter for 1.25Gb/s Ethernet PON applications [passive optical networks]Yong-Hun Oh, Quan Le, Sang-Gug Lee 0001, Nguyen Duy Bien Yen, Ho-Yong Kang, Tae-Whan Yoo. 283-286 [doi]
• An inductor-based 52-GHz 0.18 μm SiGe HBT cascode LNA with 22 dB gainMichael Gordon, Sorin P. Voinigescu. 287-290 [doi]
• A 5 GHz fully integrated ESD-protected low-noise amplifier in 90 nm RF CMOSDimitri Linten, Steven Thijs, Mahadeva Iyer Natarajan, Piet Wambacq, Wutthinan Jeamsaksiri, Javier Ramos, Abdelkarim Mercha, Snezana Jenei, Stéphane Donnay, Stefaan Decoutere. 291-294 [doi]
• A 5 GHz CMOS low-noise amplifier with inductive ESD protection exceeding 3 kV HBMPaul Leroux, Michiel Steyaert. 295-298 [doi]
• A digital CMOS micro-hotplate array for analysis of environmentally relevant gasesUrs Frey, Markus Graf, Stefano Taschini, Kay-Uwe Kirstein, Christoph Hagleitner, Andreas Hierlemann, Henry Baltes. 299-302 [doi]
• VLSI implementation of the sphere decoding algorithmAndreas Burg, Markus Wenk, Martin Zellweger, Marc Simon Wegmueller, Norbert Felber, Wolfgang Fichtner. 303-306 [doi]
• Towards an AES crypto-chip resistant to differential power analysisNorbert Pramstaller, Frank K. Gürkaynak, Simon Haene, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner. 307-310 [doi]
• A delay-encoding-logic array processor for dynamic programming matchingMakoto Ogawa, Tadashi Shibata. 311-314 [doi]
• A power-efficient 4-PAM signaling scheme with convolutional encoder in space for chip-to-chip communicationKamran Farzan, David A. Johns. 315-318 [doi]
• Dual-level LVDS technique for reducing the data transmission lines by half of LCD driver ICDoo-Hwan Kim, Sung-Hyun Yang, Kyoung-Rok Cho. 319-322 [doi]
• Adaptive threshold scheme to operate long on-chip buses at the limit of signal integrityAtul Katoch, Manish Garg, Evert Seevinck, Harry J. M. Veendrick. 323-326 [doi]
• On-chip versus off-chip passives in multi-band radio designXinzhong Duo, Tommi Torikka, Li-Rong Zheng, Mohammed Ismail, Hannu Tenhunen. 327-330 [doi]
• A mixed-signal integrated circuit for FM-DCSK modulationManuel Delgado-Restituto, A. J. Acosta, Ángel Rodríguez-Vázquez. 331-334 [doi]
• Design of a highly integrated tuner suitable for analog and digital TV systemsRoc Berenguer, Erik Hernández, N. Rodriguez, Iosu Cendoya, Armando Munoz, Héctor Solar. 335-338 [doi]
• A 6bit, 1.2GSps low-power flash-ADC in 0.13μm digital CMOSChristoph Sandner, Martin Clara, Andreas Santner, Thomas Hartig, Franz Kuttner. 339-342 [doi]
• A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 μm CMOS [ADC applications]Simon M. Louwsma, E. J. M. van Tuijl, Maarten Vertregt, Peter C. S. Scholtens, Bram Nauta. 343-346 [doi]
• 4-Gb/s track and hold circuit using parasitic capacitance canceller [flash ADC application]Takahide Sato, Shigetaka Takagi, Nobuo Fujii, Yasuyuki Hashimoto, Kohji Sakata, Hirovuki Okada. 347-350 [doi]
• A cavity channel SESO embedded memory with low standby-power techniquesBryan Atwood, Tomoyuki Ishii, Takao Watanabe, Toshiyuki Mine, Norifumi Kameshiro, Toshiaki Sano, Kazuo Yano. 351-354 [doi]
• High-bit-rate low-power decision circuit using InP/InGaAs HBT technology [master-slave D-type flip-flop]Kiyoshi Ishii, Hideyuki Nosaka, Minoru Ida, Kenji Kurishima, Michihiro Hirata, Takatorno Enoki, Tsugumichi Shibata. 355-358 [doi]
• 1-58 Gb/s PRBS generator with <1.1 ps RMS jitter in InP technologyHugo Veenstra. 359-362 [doi]
• Notice of Violation of IEEE Publication PrinciplesA 10GHz SiGe OC192 frequency synthesizer using a passive feed-forward loop filter and a half rate oscillatorA. Maxim. 363-366 [doi]
• A 10 GHz frequency synthesiser for 802.11a in 0.18 μm CMOS [transceiver applications]N. Pavlovic, J. Gosselin, K. Mistry, D. Leenaerts. 367-370 [doi]
• A low jitter triple-band digital LC PLL in 130nm CMOSNicola Da Dalt, Edwin Thaller, Peter Gregorius, Lajos Gazsi. 371-374 [doi]
• A 0.8-8 GHz 9.7 mW analog-digital dual-loop adaptive-bandwidth DLL based multi-phase clock generatorTsung-Te Liu, Chorng-Kuang Wang. 375-378 [doi]
• Digital delay locked loop with open-loop digital duty cycle corrector for 1.2Gb/s/pin double data rate SDRAMChun-Seok Jeong, Changsik Yoo, Jae-Jin Lee, Joongsik Kih. 379-382 [doi]
• A small ripple regulated charge pump with automatic pumping control schemesSung-Eun Kim, Seong-Jun Song, Jin Kyung Kim, Sunyoung Kim, Jae-Youl Lee, Hoi-Jun Yoo. 383-386 [doi]
• A mixed-signal chip with HV-protected pins in 0.35-μm-based HV-technologyWim Van de Maele, F. Stevens, A. Huot-Marchand, B. Sekerkiran. 387-390 [doi]
• Temperature referenced supply voltage and forward-body-bias control (TSFC) architecture for minimum power consumption [ubiquitous computing processors]Goichi Ono, Masayuki Miyazaki, Hidetoshi Tanaka, Nono Ohkubo, Takayuki Kawahara. 391-394 [doi]
• A low-power clock generator for system-on-a-chip (SoC) processorsAmir M. Fahim. 395-398 [doi]
• A novel active feedback flyback [inductive load driver]Jan F. J. Wouters, Jan Sevenhans, Stefaan Van Hoogenbemt, Thierry Fernandez, Jeff Biggs, Carl Das, Steven Dupont. 399-402 [doi]
• Low temperature polycrystalline silicon TFT fingerprint sensor with integrated comparator circuitHiroyuki Hara, Mikio Sakurai, Mitsutoshi Miyasaka, Simon W.-B. Tam, Satoshi Inoue, Tatsuya Shimoda. 403-406 [doi]
• Quadrature oscillator with pre-distorted waveforms for application in MEMS-based mechanical spectrum analyserGer de Graaf, Lukas Mol, Luís A. Rocha, Edmond Cretu, Reinoud F. Wolffenbuttel. 407-410 [doi]
• High-sensitivity, high-dynamic range 768 × 576 pixel CMOS image sensorWerner Brockherde, Arndt Bußmann, Christian Nitta, Bedrich J. Hosticka, Reiner K. Wertheimer. 411-414 [doi]
• A colour 3200fps high-speed CMOS imager for endoscopy in bio-medical applicationsFelix Lustenberger, M. Lehmann, L. Cavalier, Nicolas Blanc, W. Heppner, J. Ernst, S. Gick, H. Bloss. 415-418 [doi]
• A 16×16-pixel range-finding CMOS image sensorDavid Stoppa, Luigi Viarani, Andrea Simoni, Lorenzo Gonzo, Mattia Malfatti, Gianmaria Pedretti. 419-422 [doi]
• A dual-mode low-pass filter for 802.11b/Bluetooth receiverAhmed Nader Mohieldin, Edgar Sánchez-Sinencio. 423-426 [doi]
• An integrated laser radar receiver with resonance-based timing discriminationJani Pehkonen, Juha Kostamovaara. 427-430 [doi]
• A low power highly linear 2.4 GHz CMOS receiver front-end using current amplifierIckjin Kwon, Kwyro Lee. 431-434 [doi]
• Fully integrated ultra wide band CMOS low noise amplifierChristian Grewing, Martin Friedrich, Giuseppe Li Puma, Christoph Sandner, Stefan van Waasen, Andreas Wiesbauer, Kay Winterberg. 435-438 [doi]
• A 100 MHz timing generator for impulse radio applicationsChun-Pang Wu, Hen-Wai Tsao. 439-442 [doi]
• A chopped Hall sensor with programmable "true power-on" functionMario Motz, Dieter Draxelmayr, Tobias Werth, Bernhard Forster. 443-446 [doi]
• An EMC-robust high voltage system-on-chipLuc Vander Voorde, K. Appeltans, Javier Alonso. 447-450 [doi]
• Circuit for readout and linearisation of sensor bridgesGer de Graaf, Reinoud F. Wolffenbuttel. 451-454 [doi]
• New implantable stimulator for the FES of paralyzed musclesJean-Denis Techer, Serge Bernard, Yves Bertrand, Guy Cathébras, David Guiraud. 455-458 [doi]
• An analog front-end for remote sensor applications with high input common-mode rejection including a 16bit ΣΔ ADC in 0.35μm 3.3V CMOS processEric Compagne, Stephane Maulet, Sebastien Genevey. 459-462 [doi]
• A CMOS-based tactile sensor for continuous blood pressure monitoringKay-Uwe Kirstein, Jan Sedivý, Tomi Salo, Christoph Hagleitner, Tobias Vancura, Henry Baltes. 463-466 [doi]
• A physically oriented model to quantify the dynamic noise margin [on-chip noise]Tobias Gemmeke, Tobias G. Noll. 467-470 [doi]
• A 1.35-V sense amplifier for non volatile memories based on current mode approachAntonino Conte, Gianbattista Lo Giudice, Gaetano Palumbo, Alfredo Signorello. 471-474 [doi]
• A low-swing single-ended L1 cache bus technique for sub-90nm technologiesPeter Caputa, Mark A. Anders 0001, Christer Svensson, Ram K. Krishnamurthy, Shekhar Borkar. 475-477 [doi]
• An area-efficient high-speed Reed-Solomon decoder in 0.25 μm CMOSAntonio Giuseppe Maria Strollo, Nicola Petra, Davide De Caro, Ettore Napoli. 479-482 [doi]
• A dual mode channel decoder for 3GPP2 mobile wireless communicationsChien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, Chen-Yi Lee. 483-486 [doi]
• A 2.5 Gbps - 3.125 Gbps multi-core serial-link transceiver in 0.13 μm CMOSTomas Geurts, Wim Rens, Jan Crols, Shoichiro Kashiwakura, Yuichi Segawa. 487-490 [doi]
• A 4-channel 2.5Gb/s/channel 66dBΩ inductorless transimpedance amplifier [optical receiver applications]Paul Muller, Yusuf Leblebici, Matthew K. Emsley, M. Selim Ünlü. 491-494 [doi]