Mark A. Anders 0001 - researchr alias

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Viewing Publication 1 - 13 from 13

2026

2, Fully Synthesizable, Digital Compute-in-Memory Accelerator Supporting INT8×INT8 with Zero-Point Quantization in Intel 18A TechnologyAmit Agarwal 0001, Steven K. Hsu, Mark A. Anders 0001, Arnab Raha, Deepak A. Mathaikutty, Ram Krishnamurthy 0001. isscc 2026: 528-530 [doi]

2023

A 7-Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOSRaghavan Kumar, Vikram B. Suresh, Sachin Taneja, Mark A. Anders 0001, Steven Hsu, Amit Agarwal 0001, Vivek De, Sanu K. Mathew. jssc, 58(4):1106-1116, 2023. [doi]

2022

On-Chip High-Resolution Timing Characterization Circuits for Memory IPsAmit Agarwal 0001, Steven Hsu, Mark A. Anders 0001, Gunjan Pandya, Ram Krishnamurthy 0001, James W. Tschanz, Vivek De. esscirc 2022: 377-380 [doi]

2.4GHz, Double-Buffered, 4kb Standard-Cell-Based Register File with Low-Power Mixed-Frequency Clocking for Machine Learning AcceleratorsSteven Hsu, Amit Agarwal 0001, Mark A. Anders 0001, Arnab Raha, Raymond Sung, Deepak Mathaikutty, Ram Krishnamurthy 0001, James W. Tschanz, Vivek De. vlsit 2022: 22-23 [doi]

A 7Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOSRaghavan Kumar, Vikram B. Suresh, Sachin Taneja, Mark A. Anders 0001, Steven Hsu, Amit Agarwal 0001, Vivek De, Sanu Mathew. vlsit 2022: 138-139 [doi]

An 8.3-to-18Gbps Reconfigurable SCA-Resistant/Dual-Core/Blind-Bulk AES Engine in Intel 4 CMOSRaghavan Kumar, Vikram B. Suresh, Mark A. Anders 0001, Steven K. Hsu, Amit Agarwal 0001, Vivek K. De, Sanu K. Mathew. isscc 2022: 1-3 [doi]

2005

2004

A low-swing single-ended L1 cache bus technique for sub-90nm technologiesPeter Caputa, Mark A. Anders 0001, Christer Svensson, Ram K. Krishnamurthy, Shekhar Borkar. esscirc 2004: 475-477 [doi]

2003

A transition-encoded dynamic bus technique for high-performance interconnectsMark A. Anders 0001, Nivruti Rai, Ram K. Krishnamurthy, Shekhar Borkar. jssc, 38(5):709-714, 2003. [doi]

A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder coreSanu Mathew, Mark A. Anders 0001, Ram K. Krishnamurthy, Shekhar Borkar. jssc, 38(5):689-695, 2003. [doi]

2002

2001

Sub-500-ps 64-b ALUs in 0.18-/spl mu/m SOI/bulk CMOS: design and scaling trendsSanu K. Mathew, Ram K. Krishnamurthy, Mark A. Anders 0001, Rafael Rios, Kaizad R. Mistry, Krishnamurthy Soumyanath. jssc, 36(11):1636-1646, 2001. [doi]

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