Table of Contents

• First demonstration of Two Metal Level Semi-damascene Interconnects with Fully Self-aligned Vias at 18MPGayle Murdoch, M. O'Toole, G. Marti, A. Pokhrel, D. Tsvetanova, S. Decoster, S. Kundu, Y. Oniki, A. Thiam, Q. T. Le, O. Varela Pedreira, Alicja Lesniewska, G. Martinez-Alanis, S. Park, Zsolt Tokei. 1-2 [doi]
• 11 Cycling of 3D GAA Nanosheet Ferroelectric FET with Stacked HfZrO2 to Homogenize Corner Field Toward Mitigate Dead Zone for High-Density eNVMC.-Y. Liao, K.-Y. Hsiang, Z.-F. Lou, H.-C. Tseng, C. Y. Lin, Z. X. Li, F.-C. Hsieh, C.-C. Wang, F. S. Chang, W.-C. Ray, Y.-Y. Tseng, Shu-Tong Chang, T.-C. Chen, M. H. Lee. 1-2 [doi]
• From System-on-Chip (SoC) to System on Multi-Chip (SoMC) architectures: Scaling integrated systems beyond the limitations of deep-submicron single chip technologiesChristopher Patrick, S. C. Song, Irfan Khan, Nader Nikfar, Matt Severson, Shree Pandey, Matt Kaiser, Manav Shah, Pat Lawlor, Deb Marich, Carina Affinito, Rajeev Jain. 1-2 [doi]
• 9 Cycles without VT Drift PenaltyZehao Lin, Mengwei Si, Peide D. Ye. 1-2 [doi]
• Holistic Patterning to Advance Semiconductor Manufacturing in the 2020s and BeyondMartin van den Brink, Anthony Yen, Paul van Wijnen, Michael Lercel, Boudewijn Sluijk. 3-7 [doi]
• A Reference-Free Phase Noise Measurement Circuit Achieving 24.2 fs Periodic Jitter Sensitivity and 275 fsrms Resolution with Background Self-CalibrationWei-Jhih Jian, Wei-Zen Chen. 8-9 [doi]
• A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitterZunsong Yang, Zule Xu, Masaru Osada, Tetsuya Iizuka. 10-11 [doi]
• A Magnetically Coupled Dual-Core 154-GHz Class-F Oscillator with -177.1 FoM and -87 dBc/Hz PN at 1-MHz Offset in a 22-nm FDSOI with Third-Harmonic ExtractionSarthak Sharma, Hao Gao, Gernot Hueber, Andrea Mazzanti. 12-13 [doi]
• A DPLL-Based Phase Modulator Achieving -46dB EVM with A Fast Two-Step DCO Nonlinearity Calibration and Non-Uniform Clock CompensationZhong Gao, Martin Fritz, Jingchu He, Gerd Spalink, Robert Bogdan Staszewski, Morteza S. Alavi, Masoud Babaie. 14-15 [doi]
• A 17-95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nmBen Keller, Rangharajan Venkatesan, Steve Dai, Stephen G. Tell, Brian Zimmer, William J. Dally, C. Thomas Gray, Brucek Khailany. 16-17 [doi]
• Audio and Image Cross-Modal Intelligence via a 10TOPS/W 22nm SoC with Back-Propagation and Dynamic Power GatingZichen Fan, Hyochan An, Qirui Zhang 0001, Boxun Xu, Li Xu 0006, Chien-Wei Tseng, Yimai Peng, Ang Cao, Bowen Liu, Changwoo Lee, Zhehong Wang, Fanghao Liu, Guanru Wang, Shenghao Jiang, Hun-Seok Kim, David T. Blaauw, Dennis Sylvester. 18-19 [doi]
• TinyVers: A 0.8-17 TOPS/W, 1.7 μW-20 mW, Tiny Versatile System-on-chip with State-Retentive eMRAM for Machine Learning Inference at the Extreme EdgeVikram Jain, Juan Sebastian P. Giraldo, Jaro De Roose, Bert Boons, Linyan Mei, Marian Verhelst. 20-21 [doi]
• 2.4GHz, Double-Buffered, 4kb Standard-Cell-Based Register File with Low-Power Mixed-Frequency Clocking for Machine Learning AcceleratorsSteven Hsu, Amit Agarwal 0001, Mark A. Anders 0001, Arnab Raha, Raymond Sung, Deepak Mathaikutty, Ram Krishnamurthy 0001, James W. Tschanz, Vivek De. 22-23 [doi]
• A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge ApplicationsChia-Fu Lee, Cheng-Han Lu, Cheng-En Lee, Haruki Mori, Hidehiro Fujiwara, Yi-Chun Shih, Tan-Li Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang. 24-25 [doi]
• A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFETAida Varzaghani, Bardia Bozorgzadeh, Jack Lam, Ankush Goel, Xiaobin Yuan, Mohamed Elzeftawi, Mehran Izad, Sudipta Sarkar, Alberto Baldisserotto, Seong-Ryong Ryu, Steven Mikes, Jeffrey Hwang, Varun Joshi, Shahrzad Naraghi, Darshan Kadia, Mohammad Ranjbar, Paul Lee, Dimitri Loizos, Sotirios Zogopoulos, Shwetabh Verma, Stefanos Sidiropoulos. 26-27 [doi]
• A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial LinksTimothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese, Matthias Brändli, Troy J. Beukema, Christian W. Baks, Jonathan E. Proesel, John F. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin. 28-29 [doi]
• 0.41-pJ/b/dB Asymmetric Simultaneous Bidirectional Transceivers With PAM-4 Forward and PAM-2 Back Channels for 5-m Automotive Camera LinkYunhee Lee, Woonghee Lee, Minkyo Shim, Soyeong Shin, Woo-seok Choi, Deog Kyoon Jeong. 30-31 [doi]
• A 9 Gb/s 1.1 Vpp Precision Single-Ended Pin Electronics Driver in 40nm CMOSPaul van der Wagt, Allan Parks, Greg Warwar, Lawrence Choi, Bradley Salz, Shih-Tun Chen, Ron Sartschev, Divyesh Gajjar. 32-33 [doi]
• A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS TechnologyZhongkai Wang, Minsoo Choi, Paul Kwon, Kyoungtae Lee, Bozhi Yin, Zhaokai Liu, Kwanseo Park, Ayan Biswas, Jaeduk Han, Sijun Du, Elad Alon. 34-35 [doi]
• A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge InferenceHechen Wang, Renzhi Liu, Richard Dorrance, Deepak Dasalukunte, Xiaosen Liu, Dan Lake, Brent R. Carlton, May Wu. 36-37 [doi]
• Neuro-CIM: A 310.4 TOPS/W Neuromorphic Computing-in-Memory Processor with Low WL/BL activity and Digital-Analog Mixed-mode Neuron FiringSangyeob Kim, Sangjin Kim, Soyeon Um, Soyeon Kim, Kwantae Kim, Hoi-Jun Yoo. 38-39 [doi]
• A 40-nm 646.6TOPS/W Sparsity-Scaling DNN Processor for On-Device TrainingZih-Sing Fu, Yu-Chi Lee, Alex Park, Chia-Hsiang Yang. 40-41 [doi]
• A 28-nm 25.1 TOPS/W Sparsity-Aware CNN-GCN Deep Learning SoC for Mobile Augmented RealityWen-Cong Huang, I-Ting Lin, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang. 42-43 [doi]
• A 640×480 Indirect Time-of-Flight Image Sensor with Tetra Pixel Architecture for Tap Mismatch Calibration and Motion Artifact SuppressionJubin Kang, Yongjae Park, Jung-Hye Hwang, Jung-Hoon Chun, Jaehyuk Choi, Seong-Jin Kim. 44-45 [doi]
• A Hybrid Indirect ToF Image Sensor for Long-Range 3D Depth Measurement under High Ambient Light ConditionsKunihiro Hatakeyama, Yu Okubo, Tomohiro Nakagome, Masahiro Makino, Hiroshi Takashima, Takahiro Akutsu, Takehide Sawamoto, Masanori Nagase, Tatsuo Noguchi, Shoji Kawahito. 46-47 [doi]
• A 4-Tap CMOS Time-of-Flight Image Sensor with In-pixel Analog Memory Array Achieving 10Kfps High-Speed Range Imaging and Depth Precision EnhancementChia-Chi Kuo, Rihito Kuroda. 48-49 [doi]
• Imager with Dynamic LSB Adaptation and Ratiometric Readout for Low-Bit Depth 5-μW Peak Power in Purely-Harvested SystemsKarim Ali Ahmed, Longyang Lin, Praveenakumar Shivappa Salamani, Massimo Alioto. 50-51 [doi]
• th-Order Truncation-Error Shaping and Input-Impedance Boosting for Biosignal AcquisitionKyeongwon Jeong, Gichan Yun, Sohmyung Ha, Minkyu Je. 52-53 [doi]
• rd Order CT SDM with a True TI NS QuantizerSeungjong Lee, Taewook Kang, Seungheun Song, Kyumin Kwon, Michael P. Flynn. 54-55 [doi]
• A 100kHz-Bandwidth 98.3dB-SNDR Noise-Shaping SAR ADC with Improved Mismatch Error Shaping and Speed-Up TechniquesKazunori Hasebe, Shinichirou Etou, Daisuke Miyazaki, Taiki Iguchi, Yuki Yagishita, Mika Takasaki, Takeru Nogamida, Hiroyuki Watanabe, Tomohiro Matsumoto, Yasushi Katayama. 56-57 [doi]
• A First-Order Continuous-Time Noise-Shaping SAR ADC with Duty-Cycled IntegratorHanyue Li, Yuting Shen, Eugenio Cantatore, Pieter Harpe. 58-59 [doi]
• st-order Δ-Δ∑ IC for Neural Signal AcquisitionXiaolin Yang, Marco Ballini, Chutham Sawigun, Wen-Yang Hsu, Jan-Willem Weijers, Jan Putzeys, Carolina Mora Lopez. 60-61 [doi]
• 2, 1.18 TΩ Segmented Duty-Cycled Resistor Replacing Pseudo-Resistor for Neural Recording Interface CircuitsCan Livanelioglu, Woojun Choi, Donghwan Kim, Jiawei Liao, Rosario M. Incandela, Giorgio Cristiano, Taekwang Jang. 62-63 [doi]
• 2 572 nW Neural Recording Micromote Using Near-Infrared Power Transfer and an RF Data UplinkGabriele Atzeni, Jongyup Lim, Jiawei Liao, Alessandro Novello, Jungho Lee, Eunseong Moon, Michael Barrow, Joseph G. Letner, Joseph T. Costello, Samuel R. Nason, Paras R. Patel, Parag G. Patil, Hun-Seok Kim, Cynthia A. Chestek, Jamie Phillips, David T. Blaauw, Taekwang Jang. 64-65 [doi]
• Helix: An Electrochemical CMOS DNA SynthesizerOmid Ghadami, Hongyu Lu, Matthew R. Chan, Mila Tan, Saeromi Chung, Sang-Heon Lee, Matthew T. Holden, Ryan de Ridder, Barry Merriman, Drew A. Hall. 66-67 [doi]
• An 8-core RISC-V Processor with Compute near Last Level Cache in Intel 4 CMOSGregory K. Chen, Phil C. Knag, Carlos Tokunaga, Ram K. Krishnamurthy. 68-69 [doi]
• Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear AlgebraAlex Carsello, Kathleen Feng, Taeyoung Kong, Kalhan Koul, Qiaoyi Liu, Jackson Melchert, Gedeon Nyengele, Maxwell Strange, Keyi Zhang, Ankita Nayak, Jeff Setter, James J. Thomas, Kavya Sreedhar, Po-Han Chen, Nikhil Bhagdikar, Zachary Myers, Brandon D'Agostino, Pranil Joshi, Stephen Richardson, Rick Bahr, Christopher Torng, Mark Horowitz, Priyanka Raina. 70-71 [doi]
• A 22nm 3.5TOPS/W Flexible Micro-Robotic Vision SoC with 2MB eMRAM for Fully-on-Chip IntelligenceQirui Zhang 0001, Hyochan An, Zichen Fan, Zhehong Wang, Ziyun Li, Guanru Wang, Hun-Seok Kim, David T. Blaauw, Dennis Sylvester. 72-73 [doi]
• A 44.3mW 62.4fps Hyperspectral Image Processor for MAV Remote SensingYu-Chen Lo, Yi-Chung Wu, Chia-Hsiang Yang. 74-75 [doi]
• MAQO: A Scalable Many-Core Annealer for Quadratic OptimizationMohammad Bagherbeik, Wentao Xu, Seyed Farzad Mousavi, Kouichi Kanda, Hirotaka Tamura, Ali Sheikholeslami. 76-77 [doi]
• A 39, 000 Subexposures/s CMOS Image Sensor with Dual-tap Coded-exposure Data-memory Pixel for Adaptive Single-shot Computational ImagingRahul Gulve, Navid Sarhangnejad, Gairik Dutta, Motasem Sakr, Don Nguyen, Roberto Rangel, Wenzheng Chen, Zhengfan Xia, Mian Wei, Nikita Gusev, Esther Y. H. Lin, Xiaonong Sun, Leo Hanxu, Nikola Katic, Ameer Abdelhadi, Andreas Moshovos, Kiriakos N. Kutulakos, Roman Genov. 78-79 [doi]
• 1200x84-pixels 30fps 64cc Solid-State LiDAR RX with an HV/LV transistors Hybrid Active-Quenching-SPAD Array and Background Digital PT CompensationToshiki Sugimoto, Tuan Thanh Ta, Koichi Kokubun, Satoshi Kondo, Tetsuro Itakura, Hisaaki Katagiri, Yutaka Ota, Mitsuhiro Sengoku, Honam Kwon, Keita Sasaki, Hiroshi Kubota, Kazuhiro Suzuki, Katsuyuki Kimura, Akihide Sai. 80-81 [doi]
• 2 In-Pixel Histogramming TDC Based on Analog Counter and Self-Calibrated Single-Slope ADCSu-Hyun Han 0001, Bumjun Kim, Seonghyeok Park, Yongjae Park, Jung-Hoon Chun, Jaehyuk Choi, Seong-Jin Kim. 82-83 [doi]
• A 184nW, 121µg/√Hz Noise Floor Triaxial MEMS Accelerometer with Integrated CMOS Readout Circuit and Variation-Compensated High Voltage MEMS BiasingYimai Peng, Seokhyeon Jeong, Kyojin Choo, Yejoong Kim, Li-Yu Chen, Rohit Rothe, Li Xu 0006, Ilya Gurin, Omid Oliaei, Vadim Tsinker, Stephen Bart, Peter Hartwell, David T. Blaauw, Dennis Sylvester. 84-85 [doi]
• A 12-bit 8GS/s RF Sampling DAC with Code-Dependent Nonlinearity Compensation and Intersegmental Current-Mismatch Calibration in 5nm FinFETByeongwoo Koo, SungHan Do, Sang-Pil Nam, Heewook Shin, Sungno Lee, Eunhye Oh, Jaemin Hong, Jung-Ho Lee, Youngjae Cho, Michael Choi, Jongshin Shin. 86-87 [doi]
• A 50 MS/s 65 dB-SNDR Pipelined SAR ADC using Capacitively Degenerated Two-Stage Dynamic AmplifierHyunchul Yoon, Teawoong Kim, Yigi Kwon, Youngcheol Chae. 88-89 [doi]
• A 0.56mW 63.6dB SNDR 250MS/s SAR ADC in 8nm FinFETJaehoon Lee 0005, Yong Lim, Jongmi Lee, Taejin Jang, Kwonwoo Kang, Jongpil Cho, Seunghyun Oh, Jongwoo Lee. 90-92 [doi]
• A 9.8-fJ/conv.-step FoMW 8b 2.5-GS/s Single-Channel CDAC-Assisted Subranging ADC with Reference-Embedded ComparatorsJia-Ching Wang, Bing-Yang Li, Tai-Haur Kuo. 92-93 [doi]
• RaM-SAR: A Low Energy and Area Overhead, 11.3fJ/conv.-step 12b 25MS/s Secure Random-Mapping SAR ADC with Power and EM Side-channel Attack ResilienceRuicong Chen, Hanrui Wang 0002, Anantha P. Chandrakasan, Hae-Seung Lee. 94-95 [doi]
• A 28-GHz Fully-Passive Retro-Reflective Phased-Array Backscattering Transceiver for 5G Network with 24-GHz Beam-Steered Wireless Power TransferMichihiro Ide, Yuasa Keito, Sena Kato, Dongwon You, Ashbir Aviat Fadila, Jian Pang, Atsushi Shirane, Kenichi Okada. 96-97 [doi]
• A 39-GHz CMOS Bi-Directional Doherty Phased-Array Beamformer Using Shared-LUT DPD with Inter-Element Mismatch Compensation Technique for 5G Base-StationZheng Li, Jian Pang, Yi Zhang 0092, Yudai Yamazaki, Qiaoyu Wang, Peng Luo, Weichu Chen, Yijing Liao, Minzhe Tang, Zhengyan Guo, Yun Wang 0008, Xi Fu, Dongwon You, Naoki Oshima, Shinichi Hori, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada. 98-99 [doi]
• A 30GHz-BW < -57dB-IM3 Direct RF Receiver Analog Front End in 16nm FinFETAthanasios Ramkaj, Adalberto Cantoni, Gabriele Manganaro, Siddharth Devarajan, Michiel Steyaert, Filip Tavernier. 100-101 [doi]
• An Ultra-compact Bidirectional T/R Folded 25.8-39.2GHz Phased-Array Transceiver Front-End with Embedded TX Power Detection/Self-calibration Path Supporting 64-/256-/512-QAM at 28-/39-GHz band for 5G in 65nm CMOS TechnologyWei Zhu, Ruitao Wang, Jian Zhang, Jiawen Wang, Chenguang Li, Yan Wang 0023. 102-103 [doi]
• Fully Integrated 2x2 MIMO Real Simultaneous Dual Band WiFi CMOS Power Amplifiers With a Single Inductor Multiple Output Supply Modulation TechniqueJi-Seon Paek, Jeongkwang Lee, Wan Kim, Jun-Suk Bang, Jongwoo Lee. 104-105 [doi]
• A Sparse Convolution Neural Network Accelerator for 3D/4D Point-Cloud Image Recognition on Low Power Mobile Device with Hopping-Index Rule Book for Efficient Coordinate ManagementQiankai Cao, Jie Gu 0001. 106-107 [doi]
• i-FlatCam: A 253 FPS, 91.49 µJ/Frame Ultra-Compact Intelligent Lensless Camera for Real-Time and Efficient Eye Tracking in VR/ARYang Zhao, Ziyun Li, Yonggan Fu, Yongan Zhang, Chaojian Li, Cheng Wan, Haoran You, Shang Wu, Xu Ouyang, Vivek Boominathan, Ashok Veeraraghavan, Yingyan Lin. 108-109 [doi]
• A 135.6Tbps/W 2R2W SRAM with 12T Logic Bit-cell with Vmin Down to 335mV Targeted for Machine-Learning Applications in 6nm FinFET CMOS TechnologyNail Etkin Can Akkaya, Gary Chan, Hung-Jen Liao, Yih Wang, Jonathan Chang. 110-111 [doi]
• Gain-Cell CIM: Leakage and Bitline Swing Aware 2T1C Gain-Cell eDRAM Compute in Memory Design with Bitline Precharge DACs and Compact Schmitt Trigger ADCsShanshan Xie, Can Ni, Pulkit Jain, Fatih Hamzaoglu, Jaydeep P. Kulkarni. 112-113 [doi]
• 2-FOMS Supply- and Temperature-Independent Time-Locked ΔΣ Capacitance-to-Digital Converter in 0.18-μm CMOSSeungyeob Baik, Taeryoung Seol, Sehwan Lee, Geunha Kim, SeongHwan Cho, Arup K. George, Junghyup Lee. 114-115 [doi]
• An Impedance-boosted Switched-capacitor Low-noise Amplifier Achieving 0.4 NEFGabriele Atzeni, Rosario M. Incandela, Youngwoo Ji, Alessandro Novello, Hesam Ghiasi, Giorgio Cristiano, Jiawei Liao, Qiuting Huang, Taekwang Jang. 116-117 [doi]
• A 90.9kS/s, 0.7nJ/conversion Hybrid Temperature Sensor in 4nm-class CMOSYou Li, David E. Duarte, Yongping Fan. 118-119 [doi]
• A 210nW BJT-based Temperature Sensor with an Inaccuracy of ±0.15°C (3σ) from -15°C to 85°CTeruki Someya, Vincent Van Hoek, Jan A. Angevare, Sining Pan, Kofi A. A. Makinwa. 120-121 [doi]
• InP HBT Technologies for sub-THz CommunicationsMiguel Urteaga, Zach Griffith, A. Arias-Purdue, A. Carter, Petra Rowell, J. Hacker, B. Brar. 122-123 [doi]
• High Efficiency 29-/38-GHz Hybrid Transceiver Front-Ends Utilizing Si CMOS and GaAs HEMT for 5G NR Millimeter-Wave Mobile ApplicationsYoungmin Kim, Hongjong Park, IlJin Lee, Joonhoi Hur, Sangmin Yoo. 124-125 [doi]
• 5G mmWave Power Amplifier and Low-Noise Amplifier in 300mm GaN-on-Si TechnologyQiang Yu, Han Wui Then, Derek Thomson, Jessica C. Chou, Jeffrey Garrett, Iwen Huang, Ibukunoluwa Momson, Surej Ravikumar, Seahee Hwangbo, Alvaro Latorre-Rey, Ananda Roy, Marko Radosavljevic, Michael Beumer, Pratik Koirala, Nicole Thomas, Nityan Nair, Heli Vora, Samuel Bader, Johann Rode, Jonathan Jensen, Said Rami. 126-127 [doi]
• A Packaged 90-to-96GHz 16-Element Phased Array with 18.8/15.8dBm Psat/OP1dB, 14.8% TX PAE in 65nm CMOS Process and +51dBm Array EIRPWei Zhu, Jian Zhang, Jiawen Wang, Ruitao Wang, Chenguang Li, Kai Wang, Yan Wang. 128-129 [doi]
• A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS FeaturesYesin Ryu, Young-Cheon Kwon, Jae-Hoon Lee, Sung-Gi Ahn, Jaewon Park, Kijun Lee, Yu Ho Choi, Han-Won Cho, Jae-San Kim, Jungyu Lee 0002, Haesuk Lee, Seung-Ho Song, Je-Min Ryu, Yeong Ho Yun, Useung Shin, Dajung Cho, Jeong Hoan Park, Jae-Seung Jeong, Suk-Han Lee, Kyounghwan Lim, Tae Sung Kim, Kyungmin Kim, Yu Jin Cha, Ik Joo Lee, Tae Kyu Byun, Han Sik Yoo, Yeong Geol Song, Myung-Kyu Lee, Sunghye Cho, Sung-Rae Kim, Ji-Min Choi, HyoungMin Kim, Soo Young Kim, Jaeyoun Youn, Myeong-O. Kim, Kyomin Sohn, Sangjoon Hwang, Jooyoung Lee. 130-131 [doi]
• 2 at 0.85VHyunjin Shin, Sangkyung Won, Dohui Kim, ByungHun Choi, Gyusung Kim, Myeonghee Oh, Jaeseung Choi 0001, Jongwook Kye. 132-133 [doi]
• A 22nm 32Mb Embedded STT-MRAM Macro Achieving 5.9ns Random Read Access and 5.8MB/s Write Throughput at up to Tj of 150 °CTakahiro Shimoi, Ken Matsubara, Tomoya Saito, Tomoya Ogawa, Yasuhiko Taito, Yoshinobu Kaneda, Masayuki Izuna, Koichi Takeda, Hidenori Mitani, Takashi Ito, Takashi Kono. 134-135 [doi]
• A High Output Power 1V Charge Pump and Power Switch for Configurable, In-Field-Programmable Metal eFuse on Intel 4 Logic TechnologyStafford Hutchins, Jiabo Li, Atresh Sanne, Zhanping Chen, Mohammad M. Hasan, Uddalak Bhattacharya, Eric Karl, Jaydeep P. Kulkarni. 136-137 [doi]
• A 7Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOSRaghavan Kumar, Vikram B. Suresh, Sachin Taneja, Mark A. Anders 0001, Steven Hsu, Amit Agarwal 0001, Vivek De, Sanu Mathew. 138-139 [doi]
• On-Chip Laser Voltage Probing Attack Detection with 100% Area Coverage at Above/Below the Bandgap Wavelength and Fully-Automated DesignHui Zhang, Longyang Lin, Qiang Fang, Massimo Alioto. 140-141 [doi]
• An Automotive ASIL-D Safety Mechanism in ADC and DAC for Communication ApplicationKyung-Hoon Lee, Jinwoo Park, Younghyo Park, Byeongwoo Koo, SungHan Do, Woongtaek Lim, Sungno Lee, Hyochul Shin, Eunhye Oh, Youngjae Cho, Michael Choi, Jongshin Shin. 142-143 [doi]
• Fully-Digital Broadband Calibration-Less Impedance Monitor for Probe Insertion Detection against Power Analysis AttacksViveka Konandur Rajanna, Himadri Singh Raghav, Tianqi Wang, Massimo Alioto. 144-145 [doi]
• An FLL-Based Clock Glitch Detector for Security Circuits in a 5nm FINFET ProcessSanquan Song, Stephen G. Tell, Brian Zimmer, Sudhir S. Kudva, Nikola Nedovic, C. Thomas Gray. 146-147 [doi]
• A 40-Gb/s/pin Low-Voltage POD Single-Ended PAM-4 Transceiver with Timing Calibrated Reset-less Slicer and Bidirectional T-Coil for GDDR7 ApplicationHyunsub Norbert Rie, Chang-Soo Yoon, Jindo Byun, Sucheol Lee, Garam Kim, Joohwan Kim, Junyoung Park, Hyunyoon Cho, Youngdo Um, Hyungmin Jin, Kwangseob Shin, Minsu Jung, Go-Eun Cha, MinJae Lee, Youngmin Kim, Byeori Han, Yuseong Jeon, Jisun Lee, Eunseok Shin, Hyuk-jun Kwon, Youngdon Choi, Jung Hwan Choi, Hyungjong Ko. 148-149 [doi]
• A 68.7-fJ/b/mm 375-GB/s/mm Single-Ended PAM-4 Interface with Per-Pin Training Sequence for the Next-Generation HBM ControllerJung Hun Park, Kwang-Hoon Lee, Yongjae Lee, Jung-Woo Sull, Yoonho Song, SangHee Lee, Hyeonseok Lee, Hoyeon Cho, Jonghyun Oh, Han-Gon Ko, Deog Kyoon Jeong. 150-151 [doi]
• A Low Power TSV I/O with Data Rate up to 10 Gb/s for Next Generation HBMJi-Young Kim, Taeryeong Kim, Jeonghyeok You, Ki-Ryong Kim, Byoung-Mo Moon, Kyomin Sohn, Seong-Ook Jung. 152-153 [doi]
• A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOSYoshinori Nishi, John W. Poulton, Xi Chen 0033, Sanquan Song, Brian Zimmer, Walker J. Turner, Stephen G. Tell, Nikola Nedovic, John M. Wilson 0002, William J. Dally, C. Thomas Gray. 154-155 [doi]
• A 25.78125Gbps Bi-directional Transceiver with Framed-Pulsewidth Modulation (FPWM) for Extended Reach Optical Links in 28nm CMOSWoohyun Kwon, Hyosup Won, Taeho Kim, Ha-Il Song, Hanho Choi, Sejun Jeon, Soon-Won Kwon, Huxian Jin, Jun-Gi Jo, Tai Young Kim, Jake Eu, Jinho Park, Hyeon-Min Bae. 156-157 [doi]
• A 286nW, 103V High Voltage Generator and Multiplexer for Electrostatic Actuation in Programmable MatterYimai Peng, Gordy Carichner, Yejoong Kim, Li-Yu Chen, Rémy Tribhout, Benoît Piranda, Julien Bourgeois, David T. Blaauw, Dennis Sylvester. 158-159 [doi]
• A Shared-Inductor Structure-Reconfigurable Regulating Rectifier (SR-RR) Enabling 6.78-MHz AC-DC Rectification and 1-MHz DC-DC Energy RecyclingFu-Bin Yang, Dao-Han Yao, Po-Hung Chen. 160-161 [doi]
• A Scalable Standing-Wave-Oscillator-based Imager with Near-Field-Modulated Pixels Achieving 64% Filling Factor for RF Intraoperative ImagingJun-Chau Chien, Zong-Jun Cheng, Shu-Yan Chuang, Hsiu-Cheng Yeh, Guan-Yu Huang, Hung-Yu Hou, Yi-Ting Chen, Wei-Yang Weng, Chi-Yang Tseng, Liang-In Lin. 162-163 [doi]
• 3 Battery-Less Crystal-Less Neural-Recording SoC Achieving 1.6cm Backscattering Range with 2mm×2mm On-Chip AntennaChanggui Yang, Yunshan Zhang, Ziyi Chang, Zhuhao Li, Tianyu Zheng, Yuxuan Luo, Shaomin Zhang, Kedi Xu, Gang Pan 0001, Bo Zhao. 164-165 [doi]
• Palm-sized LiDAR module with III/V-on-Si optical phased arrayKyunghyun Son, Dongjae Shin, Jisan Lee, Bongyong Jang, Dongsik Shim, Hyunil Byun, Chang Bum Lee, Yongchul Cho, Tatsuhiro Otsuka, Changgyun Shin, Inoh Hwang, Eunkyung Lee, Kyoungho Ha, Hyuck Choo. 166-167 [doi]
• An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOSSerdar S. Yonar, Pier Andrea Francese, Matthias Brändli, Marcel A. Kossel, Thomas Morf, Jonathan E. Proesel, Sergey V. Rylov, Herschel A. Ainspan, Martin Cochet, Zeynep Toprak Deniz, Timothy O. Dickson, Troy J. Beukema, Christian W. Baks, Michael P. Beakes, John F. Bulzacchelli, Young-Ho Choi, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin. 168-169 [doi]
• A 6.0mW 3.8GS/s 7b VTC/TDC-Assisted Interleaved SAR ADC with 13GHz ERBWAmy Whitcombe, Chun Lee, Asma Kuriparambil Thekkumpate, Somnath Kundu, Jaykant Timbadiya, Abhishek Agrawal, Brent R. Carlton, Peter Sagazio, Stefano Pellerano, Christopher D. Hull. 170-171 [doi]
• A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFETKyoung-Jun Moon, Dong-Ryeol Oh, Young-Hyo Park, Kyung-Hoon Lee, Sun-Jae Park, Sung-No Lee, Hee-Chang Hwang, Hyo-Chul Shin, Young-Jae Cho, Michael Choi, Jongshin Shin. 172-173 [doi]
• A Relative-Prime Rotation Based Fully On-Chip Background Skew Calibration for Time-Interleaved ADCsDong-Jin Chang, Seung-Tak Ryu. 174-175 [doi]
• A 90.4% Peak Efficiency 48V/1V Three-Level Hybrid Dickson Converter with Gradient Descent Run-Time Optimizer and GaN/Si Hybrid ConversionMinxiang Gong, Xin Zhang, Arijit Raychowdhury. 176-177 [doi]
• A 90.7% 4-W 3P4S Hybrid Switching Converter Using Adaptive VCF Rebalancing Technique and Switching Node Dual-Edge tdead Modulation for Extreme 48V/1V Direct DC-DC ConversionYuanqing Huang, Yogesh Ramadass, Dongsheng Brian Ma. 178-179 [doi]
• A 5.6W-Power 96.6%-Efficiency Boost-Oriented SIDO Step-Up/Down DC-DC Converter Embedding Buck Conversion with an Energy-Balancing CapacitorGyeong-Gu Kang, Ji-Hun Lee, Se-un Shin, Gyu-Hyeong Cho, Hyun-Sik Kim. 180-181 [doi]
• A Monolithic 48V-to-1V 10A Quadruple Step-Down DC-DC Converter with Hysteretic Copied On-Time 4-Phase Control and 2× Slew Rate All-Hysteretic ModeHyun-Ki Han, Min-Woo Ko, Jeong-Hyun Cho, Gyeong-Gu Kang, Seok-Tae Koh, Hong-Hyun Bae, Hyun-Sik Kim. 182-183 [doi]
• 2 Audio Analog Feature Extractor based on Time-Mode Analog Filterbank Interpolation and Time-Mode Analog RectificationSubhajit Ray, Peter R. Kinget. 184-185 [doi]
• Common-mode Stable Multilevel Output Stage with EMI Reduction Feedback Loop for Class-D audio AmplifierNaoaki Nishimura, Atsushi Matamura, Preston Birdsong, Shaolong Liu, Abhishek Bandyopadhyay, Mariana T. Markova, Rajeev Morajkar. 186-187 [doi]
• A Single-Clock-Phase Sense Amplifier Architecture with 9x Smaller Clock-to-Q Delay Compared to the StrongARM & 6.3dB Lower Noise Compared to Double-TailXiaohui Lin, Mohamed Megahed, Tejasvi Anand. 188-189 [doi]
• A 3nm GAAFET Analog Assisted Digital LDO with High Current Density for Dynamic Voltage Scaling Mobile ApplicationsSeki Kim, Hyongmin Lee, Yongjin Lee, Dongha Lee, Byeongbae Lee, Jahoon Jin, Susie Kim, Miri Noh, Kwonwoo Kang, Sangho Kim, Takahiro Nomiyama, Ji-Seon Paek, Jongwoo Lee. 190-191 [doi]
• Fully Integrated Voltage Regulators with Package-Embedded Inductors for Heterogeneous 3D-TSV-Stacked System-in-Package with 22nm CMOS Active Silicon Interposer Featuring Self-Trimmed, Digitally Controlled ON-Time Discontinuous Conduction Mode (DCM) OperationNachiket V. Desai, Harish K. Krishnamurthy, Suhwan Kim, Christopher Schaef, Sheldon Weng, Beomseok Choi, William J. Lambert, Krishnan Ravichandran, James W. Tschanz, Vivek De. 192-193 [doi]
• A 97.6%-Efficient 1-2MHz Hysteretic Buck Converter with 7V/μs DVS-Rate Enabled by Isosceles-Triangular Shunt Current Push-Pull TechniqueHong-Hyun Bae, Jeong-Hyun Cho, Gyeong-Gu Kang, Yousung Park, Hyun-Sik Kim. 194-195 [doi]
• 2 79.1%-Efficiency 200MHz Multi-Phase Buck Converter with Flying-Capacitor-Based Inter-Inductor Current Balancing TechniqueJeong-Hyun Cho, Hong-Hyun Bae, Gyu-Wan Lim, Tae-Hwang Kong, Jun Hyeok Yang, Hyun-Sik Kim. 196-197 [doi]
• 2 Power Management Unit for Implantable Electroceutical Device with a 91.4 % Peak Efficiency Buck-based Hybrid Step-up and -down MISIMO ConverterYeunhee Huh, ChiSung Bae, Hankyu Lee, Sang Joon Kim. 198-199 [doi]
• A 96.5%-Power-Efficiency Hybrid Buck-Boost Photovoltaic Energy Harvester Employing Adaptive FOCV MPPT Control for >98% MPPT Efficiency Across a 10, 000× Dynamic RangePhan Dang Hung, Hongseok Shin, Yechan Park, Nguyen Kim Hoang, Donghee Cho, Sohmyung Ha, Chul Kim, Minkyu Je. 200-201 [doi]
• A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFETKuan-Yu Chen, Chi-Sheng Yang, Yu-Hsiu Sun, Chien-Wei Tseng, Morteza Fayazi, Xin He, Siying Feng, Yufan Yue, Trevor N. Mudge, Ronald G. Dreslinski, Hun-Seok Kim, David T. Blaauw. 202-203 [doi]
• 2 Cost-Efficient Large-List SCL Polar Decoder Using Fully-Reusable LLR Buffers in 28nm CMOS TechnologyDongyun Kam, Byeong Yong Kong, Youngjoo Lee. 204-205 [doi]
• Non-linear CNN-based Read Channel for Hard Disk Drive with 30% Error Rate Reduction and Sequential 200Mbits/second Throughput in 28nm CMOSYuwei Qin, Ruben Purdy, Alec Probst, Ching-Yi Lin, Jian-Gang Jimmy Zhu. 206-207 [doi]
• NetFlex: A 22nm Multi-Chiplet Perception Accelerator in High-Density Fan-Out Wafer-Level PackagingTeyuh Chou, Wei Tang 0010, Mihai D. Rotaru, Chester Liu, Rahul Dutta, Sharon Lim Pei Siang, David Ho Soon Wee, Surya Bhattacharya, Zhengya Zhang. 208-209 [doi]
• NanoWattch: A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance ScalingDaniel S. Truesdell, Xinjian Liu, Jacob Breiholz, Shourya Gupta, Shuo Li 0008, Benton H. Calhoun. 210-211 [doi]
• Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS TechnologyYusung Kim 0002, Clifford Ong, Anandkumar Mahadevan Pillai, Harish Jagadeesh, Gwanghyeon Baek, Iqbal Rajwani, Zheng Guo, Eric Karl. 212-213 [doi]
• A 14-nm Low Voltage SRAM with Charge-Recycling and Charge Self-Saving Techniques for Low-Power ApplicationsKeonhee Cho, Giseok Kim, Ji Sang Oh, Ki-Ryong Kim, Changsu Sim, Younmee Bae, Mijung Kim, Sangyeop Baeck, Taejoong Song, Seong-Ook Jung. 214-215 [doi]
• Co-Optimization of SRAM Circuits with Sequential Access Patterns in a 7nm SoC Achieving 58% Memory Energy Reduction for AR ApplicationsDaniel H. Morris, Huichu Liu, Tony F. Wu, H. Ekin Sumbul, Elnaz Ansari, Alexandre Barachant, Jonathan Reid, Edith Beigné. 216-217 [doi]
• 4nm Voltage Auto-Tracking SRAM Pulse Generator with Fully RC Optimized Row Auto-Tracking Write Assist CircuitsInhak Lee, Dongwook Seo, Yunrong Li, Mijoung Kim, Sangyeop Baeck. 218-219 [doi]
• Experimental demonstration of novel scheme of HZO/Si FeFET reservoir computing with parallel data processing for speech recognitionE. Nako, Kasidit Toprasertpong, Ryosho Nakane, M. Takenaka, S. Takagi. 220-221 [doi]
• 2) Implemented by 3D Dynamic Memristor Array for Temporal Signal ProcessingWenxuan Sun, Woyu Zhang, Jie Yu, Yi Li, Zeyu Guo, Jinru Lai, Danian Dong, Xu Zheng, Fei Wang, Shaoyang Fan, Xiaoxin Xu, Dashan Shang, Ming Liu. 222-223 [doi]
• Few-shot graph learning with robust and energy-efficient memory-augmented graph neural network (MAGNN) based on homogeneous computing-in-memoryWoyu Zhang, Shaocong Wang, Yi Li, Xiaoxin Xu, Danian Dong, Nanjia Jiang, Fei Wang, Zeyu Guo, Renrui Fang, Chunmeng Dou, Kai Ni, Zhongrui Wang, Dashan Shang, Ming Liu. 224-225 [doi]
• A Novel Ambipolar Ferroelectric Tunnel FinFET based Content Addressable Memory with Ultra-low Hardware Cost and High Energy Efficiency for Machine LearningJin Luo, Weikai Xu, Boyi Fu, Zheru Yu, Mengxuan Yang, Yiqing Li, Qianqian Huang, Ru Huang. 226-227 [doi]
• A 3V 15b 157μW Cryo-CMOS DAC for Multiplexed Spin-Qubit BiasingLuc Enthoven, Job van Staveren, Jiang Gong, Masoud Babaie, Fabio Sebastiano. 228-229 [doi]
• Scalable 1.4 μW cryo-CMOS SP4T multiplexer operating at 10 mK for high-fidelity superconducting qubit measurementsRohith Acharya, Anton Potocnik, Steven Brebels, Alexander Grill, Jeroen Verjauw, Tsvetan Ivanov, Daniel Perez Lozano, Danny Wan, Fahd A. Mohiyaddin, Jacques Van Damme, A. M. Vadiraj, Massimo Mongillo, Georges G. E. Gielen, Francky Catthoor, Jan Craninckx, Iuliana P. Radu, Bogdan Govoreanu. 230-231 [doi]
• A 0.31V Vmin Cryogenic SRAM in 14 nm FinFET for Quantum ComputingRajiv V. Joshi, John Timmerwilke, K. Tien, Mark Yeck, S. Chakraborty. 232-233 [doi]
• A Cryogenic CMOS Current Comparator for Spin Qubit Readout Achieving Fast Readout Time and High Current ResolutionHiroshi Fuketa, Ippei Akita, Tomohiro Ishikawa, Hanpei Koike, Takahiro Mori. 234-235 [doi]
• 13-K Tnoise Cryo-CMOS Parametric Amplifier at 80 mK for Quantum ComputersGoeun Baek, Seunghun Bae, Minki Lee, Hyuncheol Park, Kangseop Lee, Jae-Yoon Sim, Moonjoo Lee, Ho-Jin Song. 236-237 [doi]
• Computing-in-Memory with SuperFlash® memBrain™ TechnologyNhan Do, Hieu Tran, Mark Reiten. 238-239 [doi]
• BEOL Compatible Ferroelectric Routers for Run-time Reconfigurable Compute-in-Memory AcceleratorsA. Khanna, H. Ye, Y. Luo, G. Bajpai, M. San Jose, Wriddhi Chakraborty, S. Yu, Patrick Fay, Suman Datta. 240-241 [doi]
• A Thousand State Superlattice(SL) FEFET Analog Weight CellK. A. Aabrar, S. G. Kirtania, A. Lu, A. Khanna, Wriddhi Chakraborty, M. San Jose, S. Yu, Suman Datta. 242-243 [doi]
• 4 Bits/cell Hybrid 1F1R for High Density Embedded Non-Volatile Memory and its Application for Compute in MemoryW. C. Chen, F. Huang, S. Qin, Z. Yu, Q. Lin, P. C. McIntyre, S. S. Wong, H.-S. Philip Wong. 244-245 [doi]
• A Wireless Urine Detection System and Platform with Power-Efficient Electrochemical Readout ASIC and ABTS-CNT BiosensorShuenn-Yuh Lee, Hao-Yun Lee, Ding-Siang Ciou, Zhan-Xian Liao, Peng-Wei Huang, Yi-Ting Hsieh, Yi-Chieh Wei, Chia-Yu Lin, Meng-Dar Shieh, Ju-Yi Chen. 246-247 [doi]
• A 90-μW Penny-Sized 1.2-gram Wireless EEG Recorder with 12-Channel FDMA Transmitter for Month-Long Continuous Mental Health MonitoringCheng Chen, Joonseok Yang, Hui Wang, Zhidong Cao, Siavash Kananian, Kevin Chen, Ada S. Y. Poon. 248-249 [doi]
• A Galvanically Coupled Electron Paramagnetic Resonance Spectrometer for Deep Tissue Hypoxia DiagnosisLuya Zhang, Ali M. Niknejad. 250-251 [doi]
• e-G2C: A 0.14-to-8.31 µJ/Inference NN-based Processor with Continuous On-chip Adaptation for Anomaly Detection and ECG Conversion from EGMYang Zhao, Yongan Zhang, Yonggan Fu, Xu Ouyang, Cheng Wan, Shang Wu, Anton Banta, Mathews M. John, Allison Post, Mehdi Razavi, Joseph R. Cavallaro, Behnaam Aazhang, Yingyan Lin. 252-253 [doi]
• Unleash Scaling Potential of 3D NAND with Innovative Xtacking® ArchitectureZongliang Huo, Weihua Cheng, Simon Yang. 254-255 [doi]
• (Why do we need) Wireless Heterogeneous Integration (anyway?)M. Peeters, S. Sinha, Xiao Sun, Claude Desset, Giuseppe Gramegna, John Slabbekoorn, Pieter Bex, N. Pinho, Tomas Webers, Dimitrios Velenis, A. Miller, Nadine Collaert, Geert Van der Plas, Eric Beyne, M. Huynen, R. Broucke. 256-257 [doi]
• SoIC_H Technology for Heterogenous System IntegrationChuei-Tang Wang, Chia-Chai Lin, Chih-Hsin Lu, Wei-Ting Chen, Chung-Hao Tsai, Douglas C. H. Yu. 258-259 [doi]
• 5.12 Tbps Co-Packaged FPGA and Silicon Photonics Interconnect I/OKaveh Hosseini, Edwin Kok, Sergey Y. Shumarayev, Daniel Jeong, Allen Chan, Austin Katzin, Songtao Liu, Radek Roucka, Manan Raval, Minh Mac, Chia-Pin Chiu, Thungoc Tran, Kumar Abhishek Singh, Sangeeta Raman, Yanjing Ke, Chen Li, Li-Fan Yang, Paulo Chao, Haiwei Lu, Fernando Luna, Xiaoqian Li, Tim Tri Hoang, Arnab Sarkar, Asako Toda, Ravi Mahajan, Nitin Deshpande, Conor O'Keeffe, Uma Krishnamoorthy, Vladimir Stojanovic, Christopher Madden, Chong Zhang, Matthew Sysak, Pavan Bhargava, Chen Sun 0003, Mark Wade. 260-261 [doi]
• An Embedded Multi-Die Active Bridge (EMAB) Chip for Rapid-Prototype Programmable 2.5D/3D Packaging TechnologyJie Zhang, Wei Lu, Po-Tsang Huang, Sih-Han Li, Tsung-Yi Hung, Shih-Hsien Wu, Ming-Ji Dai, I-Shan Chung, Wen-Chao Chen, Chin-Hung Wang, Shyh-Shyuan Sheu, Hung-Ming Chen, Kuan-Neng Chen, Wei-Chung Lo, Chih-I Wu. 262-263 [doi]
• An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute EngineJustin M. Correll, Lu Jie, Seungheun Song, Seungjong Lee, Junkang Zhu, Wei Tang 0010, Luke Wormald, Jack Erhardt, Nicolas Breil, Roger Quon, Deepak Kamalanathan, Siddarth A. Krishnan, Michael Chudzik, Zhengya Zhang, Wei D. Lu, Michael P. Flynn. 264-265 [doi]
• A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arraysHongwu Jiang, Wantong Li, Shanshi Huang, Shimeng Yu. 266-267 [doi]
• A 22nm 128-kb MRAM Row/Column-Parallel In-Memory Computing Macro with Memory-Resistance Boosting and Multi-Column ADC ReadoutPeter Deaville, Bonan Zhang, Naveen Verma. 268-269 [doi]
• In-Memory Approximate Computing Architecture Based on 3D-NAND Flash MemoriesPo-Hao Tseng, Yu-Hsuan Lin, Feng-Ming Lee, Tian-Cig Bo, Yung-Chun Li, Ming-Hsiu Lee, Kuang-Yeu Hsieh, Keh-Chung Wang, Chih-Yuan Lu. 270-271 [doi]
• The Rise of Memory in the Ever-Changing AI Era - From Memory to More-Than-MemorySeok Hee Lee. 272-275 [doi]
• Semiconductor Innovations, from Device to SystemYuh-Jier Mii. 276-281 [doi]
• Intel 4 CMOS Technology Featuring Advanced FinFET Transistors optimized for High Density and High-Performance ComputingB. Sell, S. An, J. Armstrong, D. Bahr, B. Bains, R. Bambery, K. Bang, D. Basu, S. Bendapudi, D. Bergstrom, R. Bhandavat, S. Bhowmick, M. Buehler, D. Caselli, S. Cekli, Vrsk. Chaganti, Y. J. Chang, K. Chikkadi, T. Chu, T. Crimmins, G. Darby, C. Ege, P. Elfick, T. Elko-Hansen, S. Fang, C. Gaddam, M. Ghoneim, H. Gomez, S. Govindaraju, Z. Guo, Walid M. Hafez, M. Haran, M. Hattendorf, S. Hu, A. Jain, S. Jaloviar, M. Jang, J. Kameswaran, V. Kapinus, A. Kennedy, S. Klopcic, D. Krishnan, J. Leib, Y. T. Lin, N. Lindert, G. Liu, O. Loh, Y. Luo, S. Mani, M. Mleczko, S. Mocherla, P. Packan, M. Paik, A. Paliwal, R. Pandey, K. Patankar, L. Pipes, P. Plekhanov, Chetan Prasad, M. Prince, G. Ramalingam, R. Ramaswamy, J. Riley, J. R. Sanchez Perez, J. Sandford, A. Sathe, F. Shah, H. Shim, S. Subramanian, S. Tandon, M. Tanniru, D. Thakurta, T. Troeger, X. Wang, C. Ward, A. Welsh, S. Wickramaratne, J. Wnuk, S. Q. Xu, P. Yashar, J. Yaung, K. Yoon, N. Young. 282-283 [doi]
• Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power RailsAnabela Veloso, A. Jourdain, D. Radisic, R. Chen, G. Arutchelvan, B. O'Sullivan, Hiroaki Arimura, Michele Stucchi, An De Keersgieter, M. Hosseini, T. Hopf, K. D'Have, S. Wang, E. Dupuy, G. Mannaert, Kevin Vandersmissen, S. Iacovo, P. Marien, S. Choudhury, F. Schleicher, F. Sebaai, Y. Oniki, X. Zhou, A. Gupta, Tom Schram, B. Briggs, C. Lorant, E. Rosseel, Andriy Hikavyy, Roger Loo, J. Geypen, D. Batuk, G. T. Martinez, J. P. Soulie, Katia Devriendt, B. T. Chan, S. Demuynck, Gaspard Hiblot, Geert Van der Plas, Julien Ryckaert, Gerald Beyer, E. Dentoni Litta, Eric Beyne, Naoto Horiguchi. 284-285 [doi]
• A 2-Layer Transistor Pixel Stacked CMOS Image Sensor with Oxide-Based Full Trench Isolation for Large Full Well Capacity and High Quantum EfficiencyK. Zaitsu, A. Matsumoto, M. Nishida, Y. Tanaka, H. Yamashita, Y. Satake, T. Watanabe, K. Araki, N. Nei, K. Nakazawa, J. Yamamoto, M. Uehara, H. Kawashima, Y. Kobayashi, T. Hirano, K. Tatani. 286-287 [doi]
• Reliable Sub-nanosecond MRAM with Double Spin-torque Magnetic Tunnel JunctionsC. Safranski, Guohan Hu, J. Z. Sun, P. Hashemi, S. L. Brown, L. Buzi, C. P. D'Emic, E. R. J. Edwards, Eileen A. Galligan, M. G. Gottwald, O. Gunawan, S. Karimeddiny, H. Jung, J. Kim, Kenneth F. Latzko, Philip Louis Trouilloud, S. Zare, Daniel Christopher Worledge. 288-289 [doi]
• Wafer-Scale Bi-Assisted Semi-Auto Dry Transfer and Fabrication of High-Performance Monolayer CVD WS2 TransistorMing-yang Li, Ching-Hao Hsu, Shin-Wei Shen, Ang-Sheng Chou, Yuxuan Cosmi Lin, Chih-Piao Chuu, Ning Yang, Sui-An Chou, Lin-Yun Huang, Chao-Ching Cheng, Wei-Yen Woon, Szuya Liao, Chih-I Wu, Lain-Jong Li, Iuliana Radu, H.-S. Philip Wong, Han Wang. 290-291 [doi]
• Ultra-low Leakage IGZO-TFTs with Raised Source/Drain for Vt > 0 V and Ion > 30 µA/µmS. Subhechha, Nouredine Rassoul, A. Belmonte, H. Hody, Harold Dekkers, Michiel J. van Setten, Adrian Chasin, Shamin H. Sharifi, S. Sutar, L. Magnarin, Umberto Celano, H. Puliyalil, S. Kundu, M. Pak, Lieve Teugels, D. Tsvetanova, N. Bazzazian, Kevin Vandersmissen, C. Biasotto, D. Batuk, J. Geypen, J. Heijlen, Romain Delhougne, Gouri Sankar Kar. 292-293 [doi]
• Extremely Scaled Bottom Gate a-IGZO Transistors Using a Novel Patterning Technique Achieving Record High Gm of 479.5 μS/μm (VDS of 1 V) and fT of 18.3 GHz (VDS of 3 V)Chengkuan Wang, Annie Kumar, Kaizhen Han, Chen Sun, Haiwen Xu, Jishen Zhang, Yuye Kang, Qiwen Kong, Zijie Zheng, Yuxuan Wang, Xiao Gong. 294-295 [doi]
• Vertical Channel-All-Around (CAA) IGZO FET under 50 nm CD with High Read Current of 32.8 μA/μm (Vth + 1 V), Well-performed Thermal Stability up to 120 ℃ for Low Latency, High-density 2T0C 3D DRAM ApplicationKailiang Huang, Xinlv Duan, Junxiao Feng, Ying Sun, Congyan Lu, Chuanke Chen, Guangfan Jiao, Xinpeng Lin, Jinhai Shao, Shihui Yin, Jiazhen Sheng, Zhaogui Wang, Wenqiang Zhang, Xichen Chuai, Jiebin Niu, Wenwu Wang, Ying Wu, Weiliang Jing, Zhengbo Wang, Jeffrey Xu, Guanhua Yang, Di Geng, Ling Li, Ming Liu. 296-297 [doi]
• Scaling Dual-Gate Ultra-thin a-IGZO FET to 30 nm Channel Length with Record-high Gm, max of 559 µS/µm at VDS=1 V, Record-low DIBL of 10 mV/V and Nearly Ideal SS of 63 mV/decKaifei Chen, Jiebin Niu, Guanhua Yang, Menggan Liu, Wendong Lu, Fuxi Liao, Kailiang Huang, Xinlv Duan, Congyan Lu, Jiawei Wang, Lingfei Wang, Mengmeng Li, Di Geng, Chao Zhao, Guilei Wang, Nianduan Lu, Ling Li, Ming Liu. 298-299 [doi]
• Compact Modeling of IGZO-based CAA-FETs with Time-zero-instability and BTI Impact on Device and Capacitor-less DRAM Retention ReliabilityJingrui Guo, Ying Sun, Lingfei Wang, Xinlv Duan, Kailiang Huang, Zhaogui Wang, Junxiao Feng, Qian Chen, Shijie Huang, Lihua Xu, Di Geng, Guangfan Jiao, Shihui Yin, Zhengbo Wang, Weiliang Jing, Ling Li, Ming Liu. 300-301 [doi]
• Multi-bit per-cell 1T SiGe Floating Body RAM for Cache Memory in Cryogenic ComputingW. Chakraborty, P. Shrestha, A. Gupta, Rakshith Saligram, Samuel Spetalnick, J. Campbell, Arijit Raychowdhury, S. Datta. 302-303 [doi]
• First Demonstration of 1-bit Erase in Vertical NAND Flash MemoryHonam Yoo, Jong-Won Back, Nam Hun Kim, Dongseok Kwon, Byung-Gook Park, Jong-Ho Lee. 304-305 [doi]
• High Performance Thermally Resistant FinFETs DRAM Peripheral CMOS FinFETs with VTH Tunability for Future MemoriesRomain Ritzenthaler, E. Capogreco, E. Dupuy, Hiroaki Arimura, J. P. Bastos, P. Favia, F. Sebaai, D. Radisic, V. T. H. Nguyen, G. Mannaert, B. T. Chan, V. Machkaoutsan, Y. Yoon, H. Itokawa, M. Yamaguchi, Y. Chen, Pierre Fazan, S. Subramanian, Alessio Spessot, E. Dentoni Litta, S. Samavedam, Naoto Horiguchi. 306-307 [doi]
• Optimal Cell Structure/Operation Design of 3D Semicircular Split-gate Cells for Ultra-high-density Flash MemoryT. Morooka, T. Ishikawa, M. Komura, T. Kato, Y. Koyama, Y. Han, Y. Sugawara, D. Kuwabara, Y. Arayashiki, A. Murayama, K. Nishiyama, K. Sugimae, T. Ogura, H. Takeda, N. Kariya, Y. Goki, S. Konuma, Y. Kamiya, H. Yamashita, H. Shiga, K. Itagaki, R. Tanaka, T. Maeda, N. Ohtani, M. Fujiwara. 308-309 [doi]
• 2) and Low Resistance Drift (~0.002 at 105°C)Asir Intisar Khan, Christopher Perez, Xiangjin Wu, Byoungjun Won, Kangsik Kim, Heungdong Kwon, Pranav Ramesh, Kathryn M. Neilson, Mehdi Asheghi, Krishna Saraswat, Zonghoon Lee, Il-Kwon Oh, H.-S. Philip Wong, Kenneth E. Goodson, Eric Pop. 310-311 [doi]
• Enhanced performance and low-power capability of SiGeAsSe-GeSbTe 1S1R phase-change memory operated in bipolar modeTaras Ravsher, Daniele Garbin, Andrea Fantini, Robin Degraeve, Sergiu Clima, Gabriele Luca Donadio, Shreya Kundu, Hubert Hody, Wouter Devulder, Jan Van Houdt, Valeri Afanas'ev, Romain Delhougne, Gouri Sankar Kar. 312-313 [doi]
• 8-Layer 3D Vertical Ru/AlOxNy/TiN RRAM with Mega-Ω Level LRS for Low Power and Ultrahigh-density MemoryShengjun Qin, Maryann C. Tung, Emma Belliveau, Shuhan Liu, Jimin Kwon, Wei-Chen Chen, Zizhen Jiang, S. Simon Wong, H.-S. Philip Wong. 314-315 [doi]
• Highly Reliable 40nm Embedded Dual-Interface-Switching RRAM Technology for Display Driver IC ApplicationsL. Zhao, Z. Chen, D. Manea, S. Li, J. Li, Y. Zhu, Z. Sui, Z. Lu. 316-317 [doi]
• Demonstration of High Endurance Capability on Mega-Bit RRAM Macro and Model of ppm Level FailuresChang-Feng Yang, Chun-Yu Wu, Meng-Chun Shih, Ming-Ta Yang, Ming-Han Yang, Yu-Tien Wu, Ta-Chun Chien, Chih-Wei Lai, Shih-Chi Tsai, Wen-Ting Chu, Arthur Hung. 318-319 [doi]
• 11) and Low Drift CharacteristicsJangseop Lee, Seonghun Kim, Sangmin Lee, Sanghyun Ban, Seongjae Heo, Donghwa Lee, Oleksandr Mosendz, Hyunsang Hwang. 320-321 [doi]
• Thermal Studies of BEOL-compatible Top-Gated Atomically Thin ALD In2O3 FETsPai-Ying Liao, Sami Alajlouni, Mengwei Si, Zhuocheng Zhang, Zehao Lin, Jinhyun Noh, Calista Wilk, Ali Shakouri, Peide D. Ye. 322-323 [doi]
• First Fire-free, Low-voltage (~1.2 V), and Low Off-current (~3 nA) SiOxTey SelectorsS. Vaziri, I. M. Datye, Elia Ambrosi, A. I. Khan, H. Kwon, C. H. Wu, C.-F. Hsu, J. Guy, T.-Y. Lee, H.-S. P. Wong, X. Y. Bao. 324-325 [doi]
• 2/V-s and1T-1RRAM Memory Cell Demonstration Memory Implications for Energy-Efficient Deep-Learning ComputingUmesh Chand, Mohamed M. Sabry Aly, Manohar Lal, Chen Chun-Kuei, Sonu Hooda, Shih-Hao Tsai, Zihang Fang, Hasita Veluri, Aaron Voon-Yew Thean. 326-327 [doi]
• 3D stackable cryogenic InGaAs HEMTs for heterogeneous and monolithic 3D integrated highly scalable quantum computing systemsJaeYong Jeong, Seong Kwang Kim, Jongmin Kim, Dae-Myeong Geum, Jisung Lee, Seung Young Park, SangHyeon Kim. 328-329 [doi]
• Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnectionsA. Vandooren, N. Parihar, Jacopo Franco, Roger Loo, H. Arimura, R. Rodriguez, F. Sebaai, S. Iacovo, Kevin Vandersmissen, W. Li, G. Mannaert, D. Radisic, E. Rosseel, Andriy Hikavyy, A. Jourdain, O. Mourey, G. Gaudin, S. Reboh, L. Le Van-Jodin, G. Besnard, C. Roda Neve, B.-Y. Nguyen, I. Radu, E. Dentoni Litta, N. Horiguchi. 330-331 [doi]
• Methodology for Active Junction Profile Extraction in thin film FD-SOI Enabling performance driver identification in 500°C devices for 3D sequential integrationTadeu Mota Frutuoso, Xavier Garros, Perrine Batude, Laurent Brunet, Joris Lacord, B. Sklenard, V. Lapras, Claire Fenouillet-Béranger, M. Ribotta, A. Magalhaes-Lucas, J. Kanyandekwe, R. Kies, G. Romano, Edoardo Catapano, Mikaël Cassé, Jose Lugo-Alvarez, P. Ferrari, Fred Gaillard. 332-333 [doi]
• Effect of Conduction Band Edge States on Coulomb-Limiting Electron Mobility in Cryogenic MOSFET OperationHiroshi Oka, Takumi Inaba, Shota Iizuka, Hidehiro Asai, Kimihiko Kato, Takahiro Mori. 334-335 [doi]
• Machine Learning Assisted Statistical Variation Analysis of Ferroelectric Transistors: From Experimental Metrology to Predictive ModelingGihun Choe, Prasanna Venkatesan Ravindran, Anni Lu, Jae Hur, Maximilian Lederer, André Reck, Sarah Lombardo, Nashrah Afroze, Josh Kacher, Asif Islam Khan, Shimeng Yu. 336-337 [doi]
• Determination of Domain Wall Velocity and Nucleation Time by Switching Dynamics Studies of Ferroelectric Hafnium Zirconium OxideXiao Lyu, Pragya R. Shrestha, Mengwei Si, Panni Wang, Junkang Li, Kin P. Cheung, Shimeng Yu, Peide D. Ye. 338-339 [doi]
• Insight to Data Retention loss in ferroelectric Hf0.5Zr0.5O2 pFET and nFET from simultaneous PV and IV measurementsMd Nur K. Alam, Yusuke Higashi, Brecht Truijen, Ben Kaczer, Mihaela Ioana Popovici, Bj O'Sullivan, Philippe Roussel, Robin Degraeve, Marc M. Heyns, Jan Van Houdt. 340-342 [doi]
• Atomic visualization of the emergence of orthorhombic phase in Hf0.5Zr0.5O2 ferroelectric film with in-situ rapid thermal annealingTianjiao Xin, Yonghui Zheng, Yan Cheng, Kai Du, Yiwei Wang, Zhaomeng Gao, Diqing Su, Yunzhe Zheng, Qilan Zhong, Cheng Liu, Rong Huang, Chungang Duan, Sannian Song, Zhitang Song, Hangbing Lyu. 343-344 [doi]
• 1/2) Back-Illuminated Active-Matrix Deep UV Image Sensor by Monolithic Integration of Ga2O3 Photodetectors and Oxide Thin-Film-TransistorsYuan Qin, Congyan Lu, Zhaoan Yu, Zhihong Yao, Feihong Wu, Danian Dong, Xiaolong Zhao, Guangwei Xu, Yuhao Zhang, Shibing Long, Ling Li, Ming Liu. 345-346 [doi]
• Low-Noise Multi-Gate Pixel Transistor for Sub-Micron Pixel CMOS Image SensorsShota Kitamura, Naohiko Kimizuka, Akiko Honjo, Koichi Baba, Toshihiro Kurobe, Hideomi Kumano, Takuya Toyofuku, Kouhei Takeuchi, Shota Nishimura, Akihiko Kato, Tomoyuki Hirano, Yusuke Oike. 347-348 [doi]
• Wafer Level Pixelation of Colloidal Quantum Dot Image SensorsYunlong Li, Gauri Karve, Pawel E. Malinowski, Joo Hyoung Kim, Epimitheas Georgitzikis, Vladimir Pejovic, Myung-Jin Lim, Luis Moreno Hagelsieb, Renaud Puybaret, Itai Lieberman, Jiwon Lee, David Cheyns, Paul Heremans, Haris Osman, Deniz Sabuncuoglu Tezcan. 349-350 [doi]
• A 0.6 ㎛ Small Pixel for High Resolution CMOS Image Sensor with Full Well Capacity of 10, 000e- by Dual Vertical Transfer Gate TechnologyJungbin Yun, Seungjoon Lee, Seungwon Cha, Jihun Kim, Jeongho Lee, Hanseok Kim, Eungkyu Lee, Seonok Kim, Seunghan Hong, Hyungchae Kim, Jinsuk Huh, SungChul Kim, Kazunori Kakehi, Jae-Ho Kim, June Mo Koo, Eunsang Cho, Heegeun Jeong, Howoo Park, Kyungho Lee, JungChak Ahn, JoonSeo Yim. 351-352 [doi]
• Advanced novel optical stack technologies for high SNR in CMOS Image SensorHye Yeon Park, YunKi Lee, Jonghoon Park, HyunSeok Song, Taesung Lee, Hyung Keun Gweon, Yunji Jung, Jeongmin Bae, BoSeong Kim, Junwon Han, Seungwon Kim, Cheolsang Yoon, Jeongki Kim, ChangKeun Lee, Sehoon Yoo, Euiyeol Kim, Hyunmin Baek, Howoo Park, Bumsuk Kim, JungChak Ahn, JoonSeo Yim. 353-354 [doi]
• Memory Array Demonstration of fully integrated 1T-1C FeFET concept with separated ferroelectric MFM device in interconnect layerKonrad Seidel, David Lehninger, Raik Hoffmann, Tarek Ali, Maximilian Lederer, Ricardo Revello, Konstantin Mertens, Kati Biedermann, Yukai Shen, Defu Wang, Matthias Landwehr, Andreas Heinig, Thomas Kämpfe, Hannes Mähne, Kerstin Bernert, Steffen Thiem. 355-356 [doi]
• Experimental Demonstration of An Inversion-Type Ferroelectric Capacitive Memory and its 1 kbit Crossbar Array Featuring High CHCS/CLCS, Fast Speed, and Long RetentionZuopu Zhou, Jiao Leming, Jiuren Zhou, Zijie Zheng, Yue Chen, Kaizhen Han, Yuye Kang, Xiao Gong. 357-358 [doi]
• 10 Cycles of Endurance, and Decade Lifetime at 103 °CE. R. Hsieh, J. K. Chang, T. Y. Tang, Y. J. Li, C. W. Liang, M. Y. Lin, S.-Y. Huang, C. J. Su, J.-C. Guo, Steve S. Chung. 359-360 [doi]
• Interfacial-Layer Design for Hf1-xZrxO2-Based FTJ Devices: From Atom to ArrayH.-L. Chiang, J. F. Wang, K. H. Lin, C.-H. Nien, J.-J. Wu, K.-Y. Hsiang, C.-P. Chuu, Y.-W. Chen, X. W. Zhang, C. W. Liu, Tahui Wang, C.-C. Wang, M. H. Lee, M. F. Chang, C. S. Chang, T.-C. Chen. 361-362 [doi]
• Standard Cell Design Optimization with Advanced MOL Technology in 3nm GAA ProcessGiyoung Yang, Hakchul Jung, Jinyoung Lim, Jaewoo Seo, Ingyum Kim, Jisu Yu, Hyeoungyu You, Jeongsoon Kong, Garoom Kim, Minjae Jeong, Chanhee Park, Sera An, Woojin Rim, Hayoung Kim, Dalhee Lee, Sanghoon Baek, Jonghoon Jung, Taejoong Song, Jongwook Kye. 363-364 [doi]
• PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitchP. Schuddinck, F. M. Bufler, Yang Xiang, A. Farokhnejad, Gioele Mirabelli, A. Vandooren, Bilal Chehab, A. Gupta, C. Roda Neve, Geert Hellings, Julien Ryckaert. 365-366 [doi]
• -3 Active Doping and Demonstration on Highly-Scaled 3D StructuresHaiwen Xu, Rami Khazaka, Jishen Zhang, Zijie Zheng, Yue Chen, Xiao Gong. 367-368 [doi]
• Comprehensive Feasibility Study of Single FIN Transistors for Scaling Both Switching Energy and Device FootprintH. Fukutome, K. Suh, W. Kim, Y. Moriyama, S. Kang, B. Eom, J. Kim, C. Yoon, W. Kwon, Y. Chung, Y. Nam, Y. Kim, S. Park, J. Park, H. J. Cho, K. Rim, S. D. Kwon. 369-370 [doi]
• Self-Heating in iN8-iN2 CMOS Logic Cells: Thermal Impact of Architecture (FinFET, Nanosheet, Forksheet and CFET) and Scaling BoostersBjorn Vermeersch, Erik Bury, Y. Xiang, Pieter Schuddinck, Krishna K. Bhuwalka, Geert Hellings, Julien Ryckaert. 371-372 [doi]
• Accurate and Fast STT-MRAM Endurance Evaluation Using a Novel Metric for Asymmetric Bipolar Stress and Deep LearningZ. Wei, W. Kim, Z. Wang, L. Hu, D. Jung, J. Zhang, Y. Huai. 373-374 [doi]
• Selective operations of multi-pillar SOT-MRAM for high density and low power embedded memoriesKaiming Cai, Simon Van Beek, Siddharth Rao, K. Fan, M. Gupta, V. D. Nguyen, Ganesh Jayakumar, G. Talmelli, S. Couet, Gouri Sankar Kar. 375-376 [doi]
• High speed (1ns) and low voltage (1.5V) demonstration of 8Kb SOT-MRAM arrayM. Y. Song, C. M. Lee, S. Y. Yang, G. L. Chen, K. M. Chen, I J. Wang, Y. C. Hsin, K. T. Chang, C.-F. Hsu, S. H. Li, J. H. Wei, T.-Y. Lee, M. F. Chang, X. Y. Bao, C. H. Diaz, S. J. Lin. 377-378 [doi]
• A 4K-400K Wide Operating-Temperature-Range MRAM Technology with Ultrathin Composite Free Layer and Magnesium SpacerMing-Chun Hong, Yao-Jen Chang, Yu-Chen Hsin, Liang-Ming Liu, Kuan-Ming Chen, Yi-Hui Su, Guan-Long Chen, Shan-Yi Yang, I-Jung Wang, SK Ziaur Rahaman, Hsin-Han Lee, Shih-Ching Chiu, Chen-Yi Shih, Chih-Yao Wang, Fang-Ming Chen, Jeng-Hua Wei, Shyh-Shyuan Sheu, Wei-Chung Lo, Minn-Tsong Lin, Chih-I Wu, Tuo-Hung Hou. 379-380 [doi]
• TMSuresh Venkatesan, James Lee, Simon Chun Kiat Goh, Brian Pile, Daniel Meerovich, Jinyu Mo, Yang Jing, Lucas Soldano, Baochang Xu, Yu Zhang, Aaron Voon-Yew Thean, Yeow Kheng Lim. 381-382 [doi]
• Monolithic 3D sequential integration realizing 1600-PPI red micro-LED display on Si CMOS driver ICJuhyuk Park, Dae-Myeong Geum, Woojin Baek, Johnson Shieh, SangHyeon Kim. 383-384 [doi]
• Low-ESL (<1 pH @ 8.5 GHz) Multi-Terminal Si Capacitor Embedded in 3D Functional Interposer for Power Delivery NetworkKyosuke Kobinata, Tatsuya Funaki, Yoshiaki Satake, Hitoshi Matsuno, Seiji Hidaka, Shunsuke Abe, Hiroyuki Ito, Chih-Cheng Hsiao, Sheng-Yi Li, Young-Suk Kim, Takayuki Ohba. 385-386 [doi]
• Room Temperature Cu-Cu Direct Bonding Using Wetting/Passivation Scheme for 3D Integration and PackagingZhong-Jie Hong, Demin Liu, Shu-Ting Hsieh, Han-Wen Hu, Ming-Wei Weng, Chih-I Cho, Jui-Han Liu, Kuan-Neng Chen. 387-388 [doi]
• Boosting the Memory Window of the BEOL-Compatible MFMIS Ferroelectric/ Anti-Ferroelectric FETs by Charge InjectionZijie Zheng, Chen Sun, Leming Jiao, Dong Zhang, Zuopu Zhou, Xiaolin Wang, Gan Liu, Qiwen Kong, Yue Chen, Kai Ni, Xiao Gong. 389-390 [doi]
• Asymmetric Double-Gate Ferroelectric FET to Decouple the Tradeoff Between Thickness Scaling and Memory WindowZhouhang Jiang, Yi Xiao, Swetaki Chatterjee, Halid Mulaosmanovic, Stefan Dünkel, Steven Soss, Sven Beyer, Rajiv Joshi, Yogesh Singh Chauhan, Hussam Amrouch, Vijaykrishnan Narayanan, Kai Ni 0004. 395-396 [doi]
• Lg = 130 nm GAA MBCFETs with three-level stacked In0.53Ga0.47As nanosheetsH.-B. Jo, I.-G. Lee, J.-M. Baek, S. T. Lee, S.-M. Choi, H.-J. Kim, H.-S. Jeong, W.-S. Park, J. H. Yoo, H. Y. Lee, D. Y. Yun, SW. Son, D.-H. Ko, T. W. Kim, H. M. Kwon, S.-K. Kim, J. G. Kim, J. Yun, T. Kim, J. H. Lee, J. H. Lee, C.-S. Shin, K.-S. Seo, D. H. Kim. 397-398 [doi]
• First Demonstration of Vertical Stacked Hetero-Oriented n-Ge (111)/p-Ge (100) CFET toward Mobility Balance EngineeringX.-R. Yu, W. H. Chang, T.-C. Hong, P.-J. Sung, A. Agarwal, G.-L. Luo, C.-T. Wu, K.-H. Kao, C. J. Su, S. W. Chang, W.-H. Lu, P.-Y. Fu, J. H. Lin, P.-H. Wu, T.-C. Cho, W. C.-Yu. Ma, D.-D. Lu, T.-S. Chao, T. Maeda, Y.-J. Lee, W.-F. Wu, W. K. Yeh, Y. H. Wang. 399-400 [doi]
• Nearly Ideal Subthreshold Swing and Delay Reduction of Stacked Nanosheets Using Ultrathin BodiesChung-En Tsai, Chun-Yi Cheng, Bo-Wei Huang, Hsin-Cheng Lin, Tao Chou, Chien-Te Tu, Yi-Chun Liu, Sun-Rong Jan, Yu-Rui Chen, Wan-Hsuan Hsieh, Kung-Ying Chiu, Shee-Jier Chueh, C. W. Liu. 401-402 [doi]
• Perspective on Low-dimensional Channel Materials for Extremely Scaled CMOSSheng-Kai Su, Edward Chen, Terry Y. T. Hung, Meng-Zhan Li, Gregory Pitner, Chao-Ching Cheng, Han Wang, Jin Cai, H.-S. Philip Wong, Iuliana P. Radu. 403-404 [doi]
• First Demonstration of Fully CMOS-compatible Non-volatile Programmable Photonic Switch Enabled by Ferroelectric-SOI Waveguide for Next Generation Photonic Integrated CircuitYue Chen, Gong Zhang, Jiuren Zhou, Zijie Zheng, Leming Jiao, Haibo Wang, Zuopu Zhou, Annie Kumar, Jishen Zhang, Yuxuan Wang, Qiwen Kong, Chen Sun, Xiao Gong. 405-406 [doi]
• First Monolithic Integration of Group IV Waveguide Photodetectors and Modulators on 300 mm Si Substrates for 2-μm Wavelength Optoelectronic Integrated CircuitHaibo Wang, Gong Zhang, Yue Chen, Jishen Zhang, Kaizhen Han, Yi-Chiau Huang, Xiao Gong. 407-408 [doi]
• First Si-Waveguide-Integrated InGaAs/InAlAs Avalanche Photodiodes on SOI PlatformJishen Zhang, Haiwen Xu, Kian Hua Tan, Satrio Wicaksono, Qiwen Kong, Gong Zhang, Yue Chen, Chen Sun, Haibo Wang, Chao Wang, Zijie Zheng, Leming Jiao, Zuopu Zhou, Charles Ci Wen Lim, Soon-Fatt Yoon, Xiao Gong. 409-410 [doi]
• Low-capacitance Ultrathin InGaAs Membrane Photodetector on Si Slot Waveguide towards Receiver-less SystemT. Akazawa, D. Wu, Kai Sumita, N. Sekine, M. Okano, Kasidit Toprasertpong, S. Takagi, Mitsuru Takenaka. 411-412 [doi]
• A sub-micron-thick InGaAs broadband (400-1700 nm) photodetectors with a high external quantum efficiency (>70%)Dae-Myeong Geum, Jinha Lim, Junho Jang, Seungyeop Ahn, Seongkwang Kim, Joonsup Shim, Bong-Ho Kim, Juhyuk Park, Woo Jin Baek, JaeYong Jeong, SangHyeon Kim. 413-414 [doi]
• Specificities of linear Si QD arrays integration and characterizationH. Niebojewski, B. Bertrand, E. Nowak, Thomas Bedecarrats, Bruna Cardoso Paz, Lauriane Contamin, P.-A. Mortemousque, V. Labracherie, L. Brevard, H. Sahin, Jean Charbonnier, C. Thomas, Myriam Assous, Mikaël Cassé, Matias Urdampilleta, Yann-Michel Niquet, F. Perruchot, Fred Gaillard, S. De Franceschi, Tristan Meunier, Maud Vinet. 415-416 [doi]
• Prospective Innovation of DRAM, Flash, and Logic Technologies for Digital Transformation (DX) EraDaewon Ha, Hyoung-Sub Kim. 417-418 [doi]
• 300 mm MOCVD 2D CMOS Materials for More (Than) Moore ScalingK. Maxey, C. H. Naylor, K. P. O'Brien, A. Penumatcha, A. Oni, C. Mokhtarzadeh, C. J. Dorow, C. Rogan, B. Holybee, T. Tronic, D. Adams, N. Arefin, A. Sen Gupta, C. C. Lin, T. Zhong, S. Lee, A. Kitamura, R. Bristol, S. B. Clendenning, U. Avci, M. Metz. 419-420 [doi]
• On the PBTI Reliability of Low EOT Negative Capacitance 1.8 nm HfO2-ZrO2 Superlattice Gate Stack on Lg=90 nm nFETsNirmaan Shanker, Li-Chen Wang, Suraj Cheema, Wenshen Li, Nilotpal Choudhury, Chenming Hu, Souvik Mahapatra, Sayeef S. Salahuddin. 421-422 [doi]
• Advanced BEOL Materials, Processes, and Integration to Reduce Line Resistance of Damascene Cu, Co, and Subtractive Ru InterconnectsTakeshi Nogami, Oleg Gluschenkov, Yasir Sulehria, Son Nguyen, Brown Peethala, Huai Huang, Hosadurga Shobha, Nick Lanzillo, Raghuveer Patlolla, Devika Sil, Andrew Simon, Daniel Edelstein, Nelson Felix, Junjun Liu, Toshiyuki Tabata, Fulvio Mazzamuto, Sebastien Halty, Fabien Rozé, Yasutoshi Okuno, Akira Uedono. 423-424 [doi]
• Impact of Material Interface Geometry on Interconnect ResistanceLee Brogan, Jon Reid. 425-426 [doi]
• Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm NodeR. Chen, Giuliano Sisto, Michele Stucchi, Anne Jourdain, Kenichi Miyaguchi, Pieter Schuddinck, P. Woeltgens, H. Lin, Naveen Kakarla, A. Veloso, Dragomir Milojevic, Odysseas Zografos, Pieter Weckx, Geert Hellings, Geert Van der Plas, Julien Ryckaert, Eric Beyne. 429-430 [doi]
• Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCOK. Serbulova, S. H. Chen, Geert Hellings, Anabela Veloso, Anne Jourdain, Dimitri Linten, J. De Boeck, Guido Groeseneken, Julien Ryckaert, Gert van der Plas, Eric Beyne, Eugenio Dentoni Litta, Naoto Horiguchi. 431-432 [doi]