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Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections

A. Vandooren, N. Parihar, Jacopo Franco, Roger Loo, H. Arimura, R. Rodriguez, F. Sebaai, S. Iacovo, Kevin Vandersmissen, W. Li, G. Mannaert, D. Radisic, E. Rosseel, Andriy Hikavyy, A. Jourdain, O. Mourey, G. Gaudin, S. Reboh, L. Le Van-Jodin, G. Besnard, C. Roda Neve, B.-Y. Nguyen, I. Radu, E. Dentoni Litta, N. Horiguchi. Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections. In IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022. pages 330-331, IEEE, 2022. [doi]

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