John F. Bulzacchelli - researchr alias

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2019

A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOSZeynep Toprak Deniz, Jonathan Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Mounir Meghelli. isscc 2019: 122-124 [doi]

Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14nm SOI CMOSMiguel E. Perez, Michael A. Sperling, Timothy E. Diemoz, John F. Bulzacchelli, Zeynep Toprak Deniz. cicc 2019: 1-4 [doi]

2018

A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOSJonathan Proesel, Zeynep Toprak Deniz, Alessandro Cevrero, Ilter Özkaya, Seongwon Kim, Daniel M. Kuchta, Sungjae Lee, Sergey V. Rylov, Herschel A. Ainspan, Timothy O. Dickson, John F. Bulzacchelli, Mounir Meghelli. jssc, 53(4):1214-1226, 2018. [doi]

2016

A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link RecalibrationTimothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Michael P. Beakes, Mounir Meghelli, Daniel J. Friedman. jssc, 51(8):1744-1755, 2016. [doi]

2015

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibrationTimothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Mounir Meghelli, Daniel J. Friedman. cicc 2015: 1-4 [doi]

A WDM-Compatible 4 × 32-Gb/s CMOS-driven electro-absorption modulator arrayB. G. Lee, Renato Rimolo-Donadio, Alexander V. Rylyakov, Jonathan E. Proesel, John F. Bulzacchelli, Christian W. Baks, Mounir Meghelli, Clint L. Schow, Anand Ramaswamy, J. E. Roth, J.-H. Shin, B. Koch, Daniel K. Sparacin, Gregory A. Fish. ofc 2015: 1-3 [doi]

A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch NetworksAlexander Rylyakov, Jonathan Proesel, Sergey V. Rylov, Benjamin G. Lee, John F. Bulzacchelli, Abhijeet Ardey, Ben Parker, Michael P. Beakes, Christian W. Baks, Clint Schow, Mounir Meghelli. jssc, 50(12):3120-3132, 2015. [doi]

22.1 A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networksAlexander Rylyakov, Jonathan Proesel, Sergey V. Rylov, Benjamin G. Lee, John F. Bulzacchelli, Abhijeet Ardey, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Clint Schow, Mounir Meghelli. isscc 2015: 1-3 [doi]

A 25 Gb/s burst-mode receiver for low latency photonic switch networksAlexander V. Rylyakov, Jonathan E. Proesel, Sergey V. Rylov, B. Lee, John F. Bulzacchelli, Abhijeet Ardey, Clint Schow, Mounir Meghelli. ofc 2015: 1-3 [doi]

2014

TM microprocessorZeynep Toprak Deniz, Michael A. Sperling, John F. Bulzacchelli, Gregory S. Still, Ryan Kruse, Seongwon Kim, David Boerstler, Tilman Gloekler, Raphael Robertazzi, Kevin Stawiasz, Tim Diemoz, George English, David Hui, Paul Muench, Joshua Friedrich. isscc 2014: 98-99 [doi]

A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technologyTimothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander Rylyakov, Benjamin D. Parker, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman. cicc 2014: 1-4 [doi]

2013

Design techniques for CMOS backplane transceivers approaching 30-Gb/s data ratesJohn F. Bulzacchelli. cicc 2013: 1-8 [doi]

2012

A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOSAnkur Agrawal, John F. Bulzacchelli, Timothy O. Dickson, Yong Liu, José A. Tierno, Daniel J. Friedman. jssc, 47(12):3220-3231, 2012. [doi]

A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOSAnkur Agrawal, John F. Bulzacchelli, Timothy O. Dickson, Yong Liu, José A. Tierno, Daniel J. Friedman. isscc 2012: 134-136 [doi]

Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout VoltageJohn F. Bulzacchelli, Zeynep Toprak Deniz, Todd M. Rasmus, Joseph A. Iadanza, William L. Bucossi, Seongwon Kim, Rafael Blanco, Carrie E. Cox, Mohak Chhabra, Christopher D. LeBlanc, Christian L. Trudeau, Daniel J. Friedman. jssc, 47(4):863-874, 2012. [doi]

An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier InterconnectsTimothy O. Dickson, Yong Liu, Sergey V. Rylov, Bing Dang, Cornelia K. Tsang, Paul S. Andry, John F. Bulzacchelli, Herschel A. Ainspan, Xiaoxiong Gu, Lavanya Turlapati, Michael P. Beakes, Benjamin D. Parker, John U. Knickerbocker, Daniel J. Friedman. jssc, 47(4):884-896, 2012. [doi]

Root cause identification of an hard-to-find on-chip power supply coupling failFranco Stellari, Thomas Cowell, Peilin Song, Michael Sorna, Zeynep Toprak Deniz, John F. Bulzacchelli, Nandita A. Mitra. itc 2012: 1-7 [doi]

2011

2009

A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOSJohn F. Bulzacchelli, Timothy O. Dickson, Zeynep Toprak Deniz, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Sergey V. Rylov, Daniel J. Friedman. isscc 2009: 368-369 [doi]

A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS TechnologyTimothy O. Dickson, John F. Bulzacchelli, Daniel J. Friedman. jssc, 44(4):1298-1305, 2009. [doi]

A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOSByungsub Kim, Yong Liu, Timothy O. Dickson, John F. Bulzacchelli, Daniel J. Friedman. jssc, 44(12):3526-3538, 2009. [doi]

A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOSYong Liu, Byungsub Kim, Timothy O. Dickson, John F. Bulzacchelli, Daniel J. Friedman. isscc 2009: 182-183 [doi]

Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applicationsAlexander Rylyakov, José A. Tierno, Herschel A. Ainspan, Jean-Olivier Plouchart, John F. Bulzacchelli, Zeynep Toprak Deniz, Daniel J. Friedman. isscc 2009: 94-95 [doi]

2007

A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFEAzita Emami-Neyestanak, Aida Varzaghani, John F. Bulzacchelli, Alexander V. Rylyakov, Chih-Kong Ken Yang, Daniel J. Friedman. jssc, 42(4):889-896, 2007. [doi]

A 7Gb/s 9.3mW 2-Tap Current-Integrating DFE ReceiverMatt Park, John F. Bulzacchelli, Michael P. Beakes, Daniel J. Friedman. isscc 2007: 230-599 [doi]

2006

2003

A superconducting bandpass delta-sigma modulator for direct analog-to-digital conversion of microwave radioJohn F. Bulzacchelli. PhD thesis, Massachusetts Institute of Technology, Cambridge, MA, USA, 2003. [doi]

2002

Superconducting bandpass /spl Delta//spl Sigma/ modulator with 2.23-GHz center frequency and 42.6-GHz sampling rateJohn F. Bulzacchelli, Hae-Seung Lee, James A. Misewich, Mark B. Ketchen. jssc, 37(12):1695-1702, 2002. [doi]

1992

A 155-MHz clock recovery delay- and phase-locked loopThomas H. Lee, John F. Bulzacchelli. jssc, 27(12):1736-1746, December 1992. [doi]

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1992

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