José A. Tierno - researchr alias

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Viewing Publication 1 - 34 from 34

2015

2014

A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technologyTimothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander Rylyakov, Benjamin D. Parker, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman. cicc 2014: 1-4 [doi]

A 28 GHz Hybrid PLL in 32 nm SOI CMOSMark A. Ferriss, Alexander Rylyakov, José A. Tierno, Herschel A. Ainspan, Daniel J. Friedman. jssc, 49(4):1027-1035, 2014. [doi]

Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF CircuitsShupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu, Benjamin D. Parker, Alberto Valdes-Garcia, Mihai A. T. Sanduleanu, José A. Tierno, Daniel J. Friedman. tcas, 61-I(8):2243-2252, 2014. [doi]

2013

An Integral Path Self-Calibration Scheme for a Dual-Loop PLLMark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander Rylyakov, Benjamin D. Parker, José A. Tierno, Aydin Babakhani, Soner Yaldiz, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Daniel J. Friedman. jssc, 48(4):996-1008, 2013. [doi]

Active Guardband Management in Power7+ to Save Energy and Maintain ReliabilityCharles Lefurgy, Alan J. Drake, Michael S. Floyd, Malcolm Allen-Ware, Bishop Brock, José A. Tierno, John B. Carter, Robert W. Berry. micro, 33(4):35-45, 2013. [doi]

A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOIYong Liu, Ping-Hsuan Hsieh, Seongwon Kim, Jae-sun Seo, Robert K. Montoye, Leland Chang, José A. Tierno, Daniel J. Friedman. isscc 2013: 400-401 [doi]

A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOSJean-Olivier Plouchart, Mark A. Ferriss, A. S. Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Larry T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman. tcas, 60-I(8):2009-2017, 2013. [doi]

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasingBodhisatwa Sadhu, Mark A. Ferriss, Arun Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li, Lawrence T. Pileggi, Ramesh Harjani, José A. Tierno, Daniel J. Friedman. jssc, 48(5):1138-1150, 2013. [doi]

Indirect performance sensing for on-chip analog self-healing via Bayesian model fusionS. Sun, F. Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, A. S. Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu, Benjamin D. Parker, Alberto Valdes-Garcia, Mihai A. T. Sanduleanu, José A. Tierno, Daniel J. Friedman. cicc 2013: 1-4 [doi]

2012

A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOSAnkur Agrawal, John F. Bulzacchelli, Timothy O. Dickson, Yong Liu, José A. Tierno, Daniel J. Friedman. isscc 2012: 134-136 [doi]

A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOSAnkur Agrawal, John F. Bulzacchelli, Timothy O. Dickson, Yong Liu, José A. Tierno, Daniel J. Friedman. jssc, 47(12):3220-3231, 2012. [doi]

A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulationSameh W. Asaad, Ralph Bellofatto, Bernard Brezzo, Chuck Haymes, Mohit Kapur, Benjamin D. Parker, Thomas Roewer, Proshanta Saha, Todd Takken, José A. Tierno. fpga 2012: 153-162 [doi]

An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOSMark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander Rylyakov, Benjamin D. Parker, Aydin Babakhani, Soner Yaldiz, Bodhisatwa Sadhu, Alberto Valdes-Garcia, José A. Tierno, Daniel J. Friedman. vlsic 2012: 176-177 [doi]

A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOSJean-Olivier Plouchart, Mihai A. T. Sanduleanu, Zeynep Toprak Deniz, Troy J. Beukema, Scott K. Reynolds, Benjamin D. Parker, Michael P. Beakes, José A. Tierno, Daniel J. Friedman. cicc 2012: 1-4 [doi]

A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOSJean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Lawrence T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman. cicc 2012: 1-4 [doi]

2011

Adaptive energy-management features of the IBM POWER7 chipMichael S. Floyd, Malcolm Allen-Ware, Karthick Rajamani, Tilman Gloekler, Bishop Brock, Pradip Bose, Alper Buyuktosunoglu, Juan C. Rubio, Birgit Schubert, Bruno Spruth, José A. Tierno, Lorena Pesantez. ibmrd, 55(3):8, 2011. [doi]

Active management of timing guardband to save energy in POWER7Charles Lefurgy, Alan J. Drake, Michael S. Floyd, Malcolm Allen-Ware, Bishop Brock, José A. Tierno, John B. Carter. micro 2011: 1-11 [doi]

A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neuronsJae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin D. Parker, Steven K. Esser, Robert K. Montoye, Bipin Rajendran, José A. Tierno, Leland Chang, Dharmendra S. Modha, Daniel J. Friedman. cicc 2011: 1-4 [doi]

Indirect phase noise sensing for self-healing voltage controlled oscillatorsSoner Yaldiz, V. Calayir, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, José A. Tierno. cicc 2011: 1-4 [doi]

2010

An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigahertzMontek Singh, José A. Tierno, Alexander Rylyakov, Sergey Rylov, Steven M. Nowick. tvlsi, 18(7):1043-1056, 2010. [doi]

2009

Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applicationsAlexander Rylyakov, José A. Tierno, Herschel A. Ainspan, Jean-Olivier Plouchart, John F. Bulzacchelli, Zeynep Toprak Deniz, Daniel J. Friedman. isscc 2009: 94-95 [doi]

2008

2007

A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) All-Static CMOS AD PLL in 65nm SOIAlexander Rylyakov, José A. Tierno, George English, Daniel J. Friedman, M. Megheli. isscc 2007: 172-173 [doi]

2003

Integrated transversal equalizers in high-speed fiber-optic systemsHui Wu, José A. Tierno, Petar K. Pepeljugoski, Jeremy Schaub, Sudhir M. Gowda, Jeffrey A. Kash, Ali Hajimiri. jssc, 38(12):2131-2137, 2003. [doi]

2002

An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertzJosé A. Tierno, Sergey Rylov, Alexander Rylyakov, Montek Singh, Steven M. Nowick. async 2002: 84 [doi]

1998

Asynchronous Circuits and Systems in Superconducting RSFQ Digital TechnologyZ. John Deng, Steve R. Whiteley, Theodore Van Duzer, José A. Tierno. async 1998: 274 [doi]

Asynchronous Parallel Prefix ComputationRajit Manohar, José A. Tierno. TC, 47(11):1244-1252, 1998.

1997

Asynchronous Transpose-Matrix ArchitecturesJosé A. Tierno, Prabhakar Kudva. iccd 1997: 423-428

1996

The energy and entropy of VLSI computationsJosé A. Tierno, Rajit Manohar, Alain J. Martin. async 1996: 188-196 [doi]

1994

A 100-MIPS GaAs Asynchronous MicroprocessorJosé A. Tierno, Alain J. Martin, Drazen Borkovic, Tak-Kwan Lee. dt, 11(2):43-49, 1994. [doi]

Low-energy asynchronous memory designJosé A. Tierno, Alain J. Martin. async 1994: 176-185 [doi]

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