Michael P. Beakes - researchr alias

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Viewing Publication 1 - 24 from 24

2023

2022

2020

2019

2016

2015

22.1 A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networksAlexander Rylyakov, Jonathan Proesel, Sergey V. Rylov, Benjamin G. Lee, John F. Bulzacchelli, Abhijeet Ardey, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Clint Schow, Mounir Meghelli. isscc 2015: 1-3 [doi]

A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch NetworksAlexander Rylyakov, Jonathan Proesel, Sergey V. Rylov, Benjamin G. Lee, John F. Bulzacchelli, Abhijeet Ardey, Ben Parker, Michael P. Beakes, Christian W. Baks, Clint Schow, Mounir Meghelli. jssc, 50(12):3120-3132, 2015. [doi]

2014

A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/OsThomas Toifl, Peter Buchmann, Troy J. Beukema, Michael P. Beakes, Matthias Braendli, Pier Andrea Francese, Christian Menolfi, Marcel A. Kossel, Lukas Kull, Thomas Morf. esscirc 2014: 455-458 [doi]

2013

A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOSJean-Olivier Plouchart, Mark A. Ferriss, A. S. Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Larry T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman. tcas, 60-I(8):2009-2017, 2013. [doi]

2012

An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier InterconnectsTimothy O. Dickson, Yong Liu, Sergey V. Rylov, Bing Dang, Cornelia K. Tsang, Paul S. Andry, John F. Bulzacchelli, Herschel A. Ainspan, Xiaoxiong Gu, Lavanya Turlapati, Michael P. Beakes, Benjamin D. Parker, John U. Knickerbocker, Daniel J. Friedman. jssc, 47(4):884-896, 2012. [doi]

A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOSJean-Olivier Plouchart, Mihai A. T. Sanduleanu, Zeynep Toprak Deniz, Troy J. Beukema, Scott K. Reynolds, Benjamin D. Parker, Michael P. Beakes, José A. Tierno, Daniel J. Friedman. cicc 2012: 1-4 [doi]

A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOSJean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Lawrence T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman. cicc 2012: 1-4 [doi]

2009

A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOSJohn F. Bulzacchelli, Timothy O. Dickson, Zeynep Toprak Deniz, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Sergey V. Rylov, Daniel J. Friedman. isscc 2009: 368-369 [doi]

2007

A 7Gb/s 9.3mW 2-Tap Current-Integrating DFE ReceiverMatt Park, John F. Bulzacchelli, Michael P. Beakes, Daniel J. Friedman. isscc 2007: 230-599 [doi]

2006

2005

A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalizationTroy J. Beukema, Michael Sorna, Karl Selander, Steven J. Zier, Brian L. Ji, Phil Murfet, James Mason, Woogeun Rhee, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes. jssc, 40(12):2633-2645, 2005. [doi]

2003

A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loopWoogeun Rhee, Herschel A. Ainspan, Sergey V. Rylov, Alexander V. Rylyakov, Michael P. Beakes, Daniel J. Friedman, Sudhir M. Gowda, Mehmet Soyuer. cicc 2003: 81-84 [doi]

2001

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