Abstract is missing.
- A semiconductor memory development and manufacturing perspectiveGreg Atwood, Scott DeBoer, Kirk Prall, Linda Somerville. 1-6 [doi]
- Slowing of Moore's law signals the beginning of Smart EverythingSehat Sutardja. 7-8 [doi]
- How chips helped discover the Higgs boson at CERNW. Snoeys. 9-19 [doi]
- Automotive electronics: Application & technology megatrendsFabio Marchio, Boris Vittorelli, Roberto Colombo. 23-29 [doi]
- Terahertz electronics: The last frontierThomas H. Lee. 30-34 [doi]
- Blocker tolerant software defined receiversHooman Darabi, David Murphy, Mohyee Mikhemar, Ahmad Mirzaei. 35-42 [doi]
- Emerging analog-to-digital convertersNima Maghari, Un-Ku Moon. 43-50 [doi]
- Ultra Low Power short range radios: Covering the last mile of the IoTKathleen Philips. 51-58 [doi]
- Time interleaved 16 bit, 250MS/s ADC using a hybrid voltage/current mode architecture with foreground calibrationYusuf Haque, Donald E. Lewis, Rex Hales, Ryan J. Kier, Tracy Johancsik, Paul T. Watkins, William Picken, Marcellus Harper, Shyam Dujari. 59-62 [doi]
- A 40MHz-BW 35fJ/step-FoM nonlinearity-cancelling two-step ADC with dual-input VCO-based quantizerPeng Zhu, Xinpeng Xing, Georges G. E. Gielen. 63-66 [doi]
- A 12b 53 mW 195 MS/s pipeline ADC with 82dB SFDR using split-ADC calibrationRohan Sehgal, Frank M. L. van der Goes, Klaas Bult. 67-70 [doi]
- A 50V input range 14bit 250kS/s ADC with 97.8dB SFDR and 80.2dB SNRIlter Ozkaya, Cagri Gurleyuk, Atilim Ergul, Arda Akkaya, Devrim Yilmaz Aksin. 71-74 [doi]
- A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOSAnnachiara Spagnolo, Bob Verbruggen, Stefano D'Amico, Piet Wambacq. 75-78 [doi]
- A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOSNereo Markulic, Kuba Raczkowski, Piet Wambacq, Jan Craninckx. 79-82 [doi]
- A 9.1-12.7 GHz VCO in 28nm CMOS with a bottom-pinning bias technique for digital varactor stress reductionBenjamin P. Hershberg, Kuba Raczkowski, Kristof Vaesen, Jan Craninckx. 83-86 [doi]
- A 600µA 32 kHz input 960 MHz output CP-PLL with 530ps integrated jitter in 28nm FD-SOI processAbhirup Lahiri, Nitin Gupta, Anand Kumar, Pradeep Dhadda. 87-90 [doi]
- An ultra-low-voltage all-digital PLL for energy harvesting applicationsJason Silver, Kannan A. Sankaragomathi, Brian P. Otis. 91-94 [doi]
- Inductively-powered direct-coupled 64-channel chopper-stabilized epilepsy-responsive neurostimulator with digital offset cancellation and tri-band radioHossein Kassiri, Arezu Bagheri, Nima Soltani, Karim Abdelhalim, Hamed Mazhab-Jafari, Muhammad Tariqus Salam, José Luis Pérez Velazquez, Roman Genov. 95-98 [doi]
- A 32-channel modular bi-directional neural interface system with embedded DSP for closed-loop operationPeng Cong, Piyush Karande, Jonathan Landes, Rob Corey, Scott Stanslaski, Wesley Santa, Randy Jensen, Forrest Pape, Dan Moran, Tim Denison. 99-102 [doi]
- A neural recorder IC with HV input multiplexer for voltage and current stimulation with 18V complianceUlrich Bihr, Jens Anders, J. Rickert, M. Schuettler, A. Moeller, K. H. Boven, Joachim Becker, Maurits Ortmanns. 103-106 [doi]
- A spectrum-equalizing analog front end for low-power electrocorticography recordingWilliam Smith, Brian Mogen, Eberhard E. Fetz, Brian Otis. 107-110 [doi]
- Printed complementary organic thin film transistors based decoder for ferroelectric memoryA. El Amraoui, Marc Bocquet, F. Barros, Jean Michel Portal, M. Charbonneau, Stéphanie Jacob, Jacqueline Bablet, Mohamed Benwadih, V. Fischer, Romain Coppard, R. Gwoziecky. 111-114 [doi]
- A 490-nA, 43-ppm/°C, sub-0.8-V supply voltage referencePinar Basak Basyurt, Devrim Yilmaz Aksin, Edoardo Bonizzoni, Franco Maloberti. 115-118 [doi]
- A 23pW, 780ppm/°C resistor-less current reference using subthreshold MOSFETsMyungjoon Choi, Inhee Lee, Tae-Kwang Jang, David Blaauw, Dennis Sylvester. 119-122 [doi]
- An improved low-power CMOS thyristor-based micro-to-millisecond delay elementBenjamin Saft, Eric Schaefer, Andre Jager, Alexander Rolapp, Eckhard Hennig. 123-126 [doi]
- A 41-mW 30-Gb/s CMOS optical receiver with digitally-tunable cascaded equalizationQuan Pan, Yipeng Wang, Zhengxiong Hou, Li Sun, Liang Wu, Wing-Hung Ki, Patrick Chiang, C. Patrick Yue. 127-130 [doi]
- A 3D-integrated 25Gbps silicon photonics receiver in PIC25G and 65nm CMOS technologiesEnrico Temporiti, Gabriele Minoia, Matteo Repossi, Daniele Baldi, Andrea Ghilioni, Francesco Svelto. 131-134 [doi]
- A DDR3/4 memory link TX supporting 24-40 Ω, 0.8-1.6 V, 0.8-5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOIMarcel A. Kossel, Christian Menolfi, Thomas Toifl, Pier Andrea Francese, Matthias Braendli, Thomas Morf, Lukas Kull, Toke Meyer Andersen, Hazar Yueksel. 135-138 [doi]
- A TDC-based 4×128 CMOS SPAD array for time-gated Raman spectroscopyIlkka Nissinen, Jan Nissinen, J. Holma, Juha Kostamovaara. 139-142 [doi]
- A 256 × 8 SPAD line sensor for time resolved fluorescence and raman sensingNikola Krstajic, Richard J. Walker, James Levitt, Simon P. Poland, David Li, Simon Ameer-Beg, Robert K. Henderson. 143-146 [doi]
- - rms offset spread and 3% rms gain spreadPiotr Maj, Pawel Grybos, Piotr Kmon, Robert Szczygiel. 147-150 [doi]
- A 50V high-speed level shifter with high dv/dt immunity for multi-MHz DCDC convertersJuergen Wittmann, Thoralf Rosahl, Bernhard Wicht. 151-154 [doi]
- A fast response integrated current-sensing circuit for peak-current-mode buck regulatorJung-Woo Ha, Bai-Sun Kong, Jung-Hoon Chun, Byeong-ha Park. 155-158 [doi]
- Bootstrap circuit with high-voltage charge storing for area efficient gate drivers in power management systemsAchim Seidel, Marco Costa, Joachim Joos, Bernhard Wicht. 159-162 [doi]
- Part-time resonant switching for light load efficiency improvement of a 3-level fully integrated buck converterWaclaw Godycki, Bo Sun, Alyssa B. Apsel. 163-166 [doi]
- Single inductor quad output switching converter with priority-scheduled program for fast transient and unlimited-load range in 40nm CMOS technologyWei-Chung Chen, Tzu-Chi Huang, Tsu-Wei Tsai, Ruei-Hong Peng, Kuei-Liang Lin, Ke-Horng Chen, Ying-Hsi Lin, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee, Li-Ren Huang, Chao-Jen Huang, Chung-Chih Hung, Chin-Long Wey, Hsin-Yu Luo. 167-170 [doi]
- A 30/35GHz phased array transmitter front-end with >+14dBm Psat and 10° phase/5-bit amplitude resolution for advanced beamformingYu Pei, Ying Chen, Domine M. W. Leenaerts, Bianca Slaats, A. Zamanifekri. 171-174 [doi]
- A 1.2V 20 dBm 60 GHz power amplifier with 32.4 dB Gain and 20 % Peak PAE in 65nm CMOSAurelien Larie, Eric Kerherve, Baudouin Martineau, Vincent Knopik, Didier Belot. 175-178 [doi]
- A 40-67GHz power amplifier with 13dBm PSAT and 16% PAE in 28 nm CMOS LPJunlei Zhao, Matteo Bassi, Andrea Bevilacqua, Andrea Ghilioni, Andrea Mazzanti, Francesco Svelto. 179-182 [doi]
- A 79GHz variable gain low-noise amplifier and power amplifier in 28nm CMOS operating up to 125°CAlaa Medra, Vito Giannini, Davide Guermandi, Piet Wambacq. 183-186 [doi]
- A 131.5GHz, -84dBm sensitivity super-regenerative receiver by zero-phase-shifter coupled oscillator network in 65nm CMOSShunli Ma, Hao Yu, Yang Shang, Wei Meng Lim, Junyan Ren. 187-190 [doi]
- A 1.5nJ/pixel super-resolution enhanced FAST corner detection processor for high accuracy ARSeongwook Park, Gyeonghoon Kim, Junyoung Park, Hoi-Jun Yoo. 191-194 [doi]
- A 0.2nJ/pixel 4K 60fps Main-10 HEVC decoder with multi-format capabilities for UHD-TV applicationsChi-Cheng Ju, Tsu-Ming Liu, Yung-Chang Chang, Chih-Ming Wang, Hue-Min Lin, Chia-Yun Cheng, Chun-Chia Chen, Min-Hao Chiu, Sheng-Jen Wang, Ping Chao, Meng-Jye Hu, Fu-Chun Yeh, Shun-Hsiang Chuang, Hsiu-Yi Lin, Ming-Long Wu, Che-Hong Chen, Chung-Hung Tsai. 195-198 [doi]
- A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector acceleratorsYunsup Lee, Andrew Waterman, Rimas Avizienis, Henry Cook, Chen Sun, Vladimir Stojanovic, Krste Asanovic. 199-202 [doi]
- An evolved EDGE PHY ASIC supporting soft-output equalization and Rx diversityHarald Kroll, Stefan Zwicky, Benjamin Weber, Christoph Roth, Christian Benkeser, Andreas Peter Burg, Qiuting Huang. 203-206 [doi]
- Time interleaved C-2C SAR ADC with background timing skew calibration in 65nm CMOSLuke Wang, Qiwei Wang, Anthony Chan Carusone. 207-210 [doi]
- An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADCYan Zhu 0001, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins. 211-214 [doi]
- A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADCBadr Malki, Bob Verbruggen, Piet Wambacq, Kazuaki Deguchi, Masao Iriguchi, Jan Craninckx. 215-218 [doi]
- A 24-µW 11-bit 1-MS/s SAR ADC with a bidirectional single-side switching techniqueLong Chen, Arindam Sanyal, Ji Ma, Nan Sun. 219-222 [doi]
- A 500MHz- 2.7 GHz 8-path weaver downconverter with harmonic rejection and embedded filteringRemko E. Struiksma, Eric A. M. Klumperink, Bram Nauta, Frank E. van Vliet. 223-226 [doi]
- A 7.86 mW +12.5 dBm in-band IIP3 8-to-320 MHz capacitive harmonic rejection mixer in 65nm CMOSChul Kim, Sohmyung Ha, Chris M. Thomas, Siddharth Joshi, Jongkil Park, Lawrence E. Larson, Gert Cauwenberghs. 227-230 [doi]
- A 3 kHz flicker noise corner, odd-phase active mixer for direct conversion receiversDongju Lee, MinJae Lee. 231-234 [doi]
- A 2.45GHz, 50uW wake-up receiver front-end with -88dBm sensitivity and 250kbps data rateCarl Bryant, Henrik Sjöland. 235-238 [doi]
- 13fJ/bit probing-resilient 250K PUF array with soft darkbit masking for 1.94% bit-error in 22nm tri-gate CMOSSudhir Satpathy, Sanu Mathew, Jiangtao Li 0001, Patrick Koeberl, Mark Anders, Himanshu Kaul, Gregory K. Chen, Amit Agarwal, Steven Hsu, Ram Krishnamurthy. 239-242 [doi]
- A 35 fJ/bit-access sub-VT memory using a dual-bit area-optimized standard-cell in 65 nm CMOSOskar Andersson, Babak Mohammadi, Pascal Andreas Meinerzhagen, Joachim Neves Rodrigues. 243-246 [doi]
- Clock and synchronization networks for a 3GHz 64bit ARMv8 8-core SoCLuca Ravezzi, Hamid Partovi, D. Wang, C. Wang, R. Cohen, M. Ashcraft, A. Yeung, Q. Harvard, Russell Homer, J. Ngai, G. Favor. 247-250 [doi]
- An on-die all-digital power supply noise analyzer with enhanced spectrum measurementsTzu-Chien Hsueh, Frank O'Mahony, Mozhgan Mansuri, Bryan Casper. 251-254 [doi]
- A 0.21-V minimum input, 73.6% maximum efficiency, fully integrated voltage boost converter with MPPT for low-voltage energy harvestersToshihiro Ozaki, Tetsuya Hirose, Takahiro Nagai, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa. 255-258 [doi]
- A 40 nA/source energy harvesting power converter for multiple and heterogeneous sourcesM. Dini, M. Filippi, Aldo Romani, Marco Tartagni, Valeria Bottarel, Giulio Ricotti. 259-262 [doi]
- An 85-mV input, 50-µs startup fully integrated voltage multiplier with passive clock boost using on-chip transformers for energy harvestingHiroshi Fuketa, Youichi Momiyama, Atsushi Okamoto, Tsuyoshi Sakata, Makoto Takamiya, Takayasu Sakurai. 263-266 [doi]
- The folding dickson converter: A step towards fully integrated wide input range capacitive DC-DC convertersAthanasios Sarafianos, Michiel Steyaert. 267-270 [doi]
- A 28nm FDSOI integrated reconfigurable switched-capacitor based step-up DC-DC converter with 88% peak efficiencyAvishek Biswas, Yildiz Sinangil, Anantha P. Chandrakasan. 271-274 [doi]
- A 5b 12.9 µW charge-redistribution phase domain ADC for low power FSK/PSK demodulationYao Liu, Duan Zhao, Yongjia Li, Wouter A. Serdijn. 275-278 [doi]
- A 13.56/402 MHz autonomous wireless sensor node with -18.2 dBm sensitivity and temperature monitoring in 0.18 /im CMOSAndré Mansano, Sumit Bagga, Wouter A. Serdijn. 279-282 [doi]
- A 5mW multi-standard Bluetooth LE/IEEE 802.15.6 SoC for WBAN applicationsGabriele Devita, Alan Chi Wai Wong, Mark Dawkins, Kostas N. Glaros, U. Kiani, Franco Lauria, V. Madaka, Okundu C. Omeni, Johannes Schiff, A. Vasudevan, L. Whitaker, S. Yu, Alison Burdett. 283-286 [doi]
- A 20Mb/s, 2.76 pJ/b UWB impulse radio TX with 11.7% efficiency in 130 nm CMOSFabio Padovan, Andrea Bevilacqua, Andrea Neviani. 287-290 [doi]
- A 60GHz transmitter in 40nm CMOS achieving mm-precision for discrete-carrier localizationParamartha Indirayanti, Tuba Ayhan, Marian Verhelst, Wim Dehaene, Patrick Reynaert. 291-294 [doi]
- Dual-slope capacitance to digital converter integrated in an implantable pressure sensing systemSechang Oh, Yoonmyung Lee, Jingcheng Wang, Zhiyoong Foo, Yejoong Kim, David Blaauw, Dennis Sylvester. 295-298 [doi]
- A highly sensitive frontend IC for very robust capacitive vortex flowmeter sensorsHanspeter Schmid, Alex Huber, Dirk Sutterlin, Werner Tanner. 299-302 [doi]
- A 533pW NEP 31×31 pixel THz image sensor based on in-pixel demodulationA. Boukhayma, Jean-Pierre Rostaing, A. Mollard, Fabrice Guellec, M. Benetti, G. Ducournau, J.-F. Lampin, Antoine Dupret, C. Enz, Michaël Tchagaspanian, J.-A. Nicolas. 303-306 [doi]
- A 26.5 nJ/px 2.64 Mpx/s CMOS vision sensor for Gaussian pyramid extractionManuel Suarez, Victor M. Brea, Jorge Fernandez-Berni, Ricardo Carmona-Galán, Diego Cabello, Ángel Rodríguez-Vázquez. 311-314 [doi]
- A Class-D amplifier powered by embedded single-inductor bipolar-output power module with low common noise and dynamic voltage boosting techniqueShin-Hao Chen, Kuei-Liang Lin, Shao Siang Ng, Ke-Horng Chen, Chin-Long Wey, Sheng Kang, Kevin Cheng, Li-Ren Huang, Chao-Jen Huang, Hsin-Yu Luo. 315-318 [doi]
- A fully integrated Class-D amplifier in 40nm CMOS with dynamic cascode bias and load current sensingVincent Binet, Francois Amiard, Emmanuel Allier, Simon Valcin, Angelo Nagari. 319-322 [doi]
- A very compact CMOS instrumentation amplifier with nearly rail-to-rail input common mode rangePaolo Bruschi, F. Del Cesta, A. N. Longhitano, Massimo Piotto, R. Simmarano. 323-326 [doi]
- Dynamic range enhanced readout circuit for a capacitive touch screen panel with current subtraction techniqueSanghyun Heo, Hyunggun Ma, Jae-Joon Kim, Franklin Bien. 327-330 [doi]
- A 195.6dBc/Hz peak FoM P-N class-B oscillator with transformer-based tail filteringMarco Garampazzi, Paulo Mendes, Nicola Codega, Danilo Manstretta, Rinaldo Castello. 331-334 [doi]
- A Class-D CMOS DCO with an on-chip LDOLuca Fanori, Thomas Mattsson, Pietro Andreani. 335-338 [doi]
- A 0.171-mW, 2.4-GHz Class-D VCO with dynamic supply voltage controlYoshiaki Yoshihara, Hideaki Majima, Ryuichi Fujimoto. 339-342 [doi]
- A pulse-driven LC-VCO with a figure-of-merit of -192dBc/HzAravind Tharayil Narayanan, Kento Kimura, Wei Deng, Kenichi Okada, Akira Matsuzawa. 343-346 [doi]
- A robust start-up Class-C CMOS VCO based on a common mode low frequency feedback loopStefano Perticaroli, Fabrizio Palma. 347-350 [doi]
- th order gm-C low-pass filter with ±3% cut-off frequency accuracy and 220MHz to 3.3GHz tuning-range in 28nm LP CMOSN. Sabatino, Gabriele Minoia, M. Roche, Daniele Baldi, Enrico Temporiti, Andrea Mazzanti. 351-354 [doi]
- 1.8GHz 3rd order lowpass filter with programmable gain in 180nm CMOSShahbaz Abbasi, Ayman Shabra. 355-358 [doi]
- A 40MHz 4th-order active-UGB-RC filter using VCO-based amplifiers with zero compensationChun-Wei Hsu, Peter R. Kinget. 359-362 [doi]
- A 33-MHz 70dB-SNR super-source-follower-based low-pass analog filterMarcello De Matteis, Alessandro Pezzotta, Stefano D'Amico, Andrea Baschirotto. 363-366 [doi]
- th order Gm-C filter with 10MHz bandwidth and 39dBm IIP3 in 65nm CMOSMohammed Abdulaziz, Markus Törmänen, Henrik Sjöland. 367-370 [doi]
- A 2.5-GHz 4.2-dB NF direct ΔΣ receiver with a frequency-translating integratorMikko Englund, Kim B. Ostman, Olli Viitala, Mikko Kaltiokallio, Kari Stadius, Jussi Ryynänen, Kimmo Koli. 371-374 [doi]
- A WCDMA/WLAN digital polar transmitter with low-noise ADPLL, wide-band PM/AM modulator and linearized PA in 65nm CMOSShiyuan Zheng, Howard C. Luong. 375-378 [doi]
- A linear 28nm CMOS digital transmitter with 2×12bit up to LO baseband sampling and -58dBc C-IM3Mark Ingels, Xiaoqiang Zhang, Kuba Raczkowski, Sungwoo Cha, Pieter Palmers, Jan Craninckx. 379-382 [doi]
- A multi-band Rel9 WCDMA/HSDPA/TDD LTE and FDD LTE transceiver with envelope trackingShahrzad Tadjpour, P. Rossi, L. Romano, R. Chokkalingam, Hamid Firouzkouhi, F. Shi, M. Leroux, Danilo Gerna, A. Venca, John Vasa, Bala Ramachandran, Brian Brunn, Alberto Pirola, Daniele Ottini, A. Milani, Enrico Sacchi, M. Behera, X. Chen, U. Decanis, Marika Tedeschi, S. DalToso, W. Eyssa, C. Cakir, C. Prakash, Y. He, Nader Damavandi, R. Srinivasan, Dan Shum, X. Fan, C. Yu, Engin Pehlivanoglu, Hossein Zarei, Aravind Loke, Gregory Uehara, Rinaldo Castello, Y. Song. 383-386 [doi]
- A SAW-less LTE transmitter with high-linearity modulator using BPF-based I/Q summingTakahiro Nakamura, Naoki Kitazawa, Kaoru Kohira, Hiroki Ishikuro. 387-390 [doi]
- A resistor-based temperature sensor for a real time clock with ±2ppm frequency stabilityPyoungwon Park, K. A. A. Makinwa, David Ruffieux. 391-394 [doi]
- 2 area-optimized thermal-diffusivity-based temperature sensor in 160-nm CMOS for SoC thermal monitoringUgur Sonmez, Rui Quan, Fabio Sebastiano, Kofi A. A. Makinwa. 395-398 [doi]
- A 50 µW, 2.1 mdeg/s/√Hz frequency-to-digital converter for frequency-output MEMS gyroscopesIgor I. Izyumin, Mitchell Kline, Yu-Ching Yeh, Burak Eminoglu, Bernhard E. Boser. 399-402 [doi]
- An eddy-current displacement-to-digital converter based on a ratio-metric delta-sigma ADCAli Fekri, Mohammad Reza Nabavi, Nikola Radeljic-Jakic, Zu-yao Chang, Michiel A. P. Pertijs, Stoyan Nihtianov. 403-406 [doi]
- A CMUT transceiver front-end with 100-V TX driver and 1-mW low-noise capacitive feedback RX amplifier in BCD-SOI technologyM. Sautto, D. Leone, Alessandro Savoia, D. Ghisu, Fabio Quaglia, Giosuè Caliano, Andrea Mazzanti. 407-410 [doi]
- A 13b SAR ADC with eye-opening VCO based comparatorKentaro Yoshioka, Hiroki Ishikuro. 411-414 [doi]
- A 2-channel 1MHz BW, 80.5 dB DR ADC using a DS modulator and zero-ISI filterDebasish Behera, Nagendra Krishnapura. 415-418 [doi]
- A 250mV 77dB DR 10kHz BW SC ΔΣ Modulator Exploiting Subthreshold OTAsZhiliang Qiao, Xiong Zhou, Qiang Li. 419-422 [doi]
- An E-Band low-noise Transformer-Coupled Quadrature VCO in 40 nm CMOSMarco Vigilante, Patrick Reynaert. 423-426 [doi]
- A novel ultra-low phase noise, programmable frequency multiplier-by-30 architecture. Application to 60-GHz frequency generationClement Jany, Alexandre Siligaris, Jose-Luis Gonzalez Jimenez, Carolynn Bernier, Pierre Vincent, Philippe Ferrari. 427-430 [doi]
- A 1V 2mW 17GHz multi-modulus frequency divider based on TSPC logic using 65nm CMOSManthena Vamshi Krishna, Anil Jain, Nasir Abdul Quadir, Paul D. Townsend, Peter Ossieur. 431-434 [doi]
- A 16 Gb/s receiver with DC wander compensated rail-to-rail AC coupling and passive linear-equalizer in 22 nm CMOSPier Andrea Francese, Thomas Toifl, Matthias Braendli, Peter Buchmann, Thomas Morf, Marcel A. Kossel, Christian Menolfi, Lukas Kull, Toke Meyer Andersen, Hazar Yueksel. 435-438 [doi]
- A 10Gb/s 4.1mW 2-IIR + 1-discrete-tap DFE in 28nm-LP CMOSShayan Shahramian, Anthony Chan Carusone. 439-442 [doi]
- A 8 Gbps blind oversampling CDR with frequency offset compensation over infinite burstAbhishek Chowdhary, Alok Kaushik, Sajal Kumar Mandal, Sanjeev Chopra, Tapas Nandy, Vivek Uppal. 443-446 [doi]
- A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay lineWoo-Rham Bae, Gyu-Seob Jeong, Kwanseo Park, Sung-Yong Cho, Yoonsoo Kim, Deog Kyoon Jeong. 447-450 [doi]
- A 3.2-GHz 1.3-mW ILO phase rotator for burst-mode mobile memory I/O in 28-nm low-leakage CMOSMarko Aleksic. 451-454 [doi]
- A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/OsThomas Toifl, Peter Buchmann, Troy J. Beukema, Michael P. Beakes, Matthias Braendli, Pier Andrea Francese, Christian Menolfi, Marcel A. Kossel, Lukas Kull, Thomas Morf. 455-458 [doi]
- A low band cellular terminal antenna impedance tuner in 130nm CMOS-SOI technologyJonas Lindstrand, Ivaylo Vasilev, Henrik Sjöland. 459-462 [doi]
- A dual-notch +27dBm Tx-power electrical-balance duplexerBarend van Liempd, Jan Craninckx, R. Singh, P. Reynaert, S. Malotaux, J. R. Long. 463-466 [doi]
- A 29.5 dBm class-E outphasing RF power amplifier with performance enhancement circuits in 45nm CMOSAritra Banerjee, Rahmi Hezar, Lei Ding, Nathan Schemm, Baher Haroun. 467-470 [doi]
- A 28 nm analog and audio mixed-signal front end for 4G/LTE Cellular System-on-ChipXicheng Jiang, Xinyu Yu, Fang Lin, Felix Cheung, Mike Inerfield, Kevin Li, Abhishek Kamath, Harsh Mehta, Jingbo Duan, Jing Yang, Gautham Krishnamurthy, Sumant Ranganathan, Darwin Cheung, Naga Radha Krishna Damaraju, Jianlong Chen, Dongtian Lu, Vinod Jayakumar, Leon Wang, Dario Soltesz, Hongwei Kong, Min Zhang, David Chang. 471-474 [doi]
- Digitally-assisted analog and analog-assisted digital design techniques for a 28 nm mobile System-on-ChipXicheng Jiang, Narayan Prasad Ramachandran, Dae Woon Kang, Chee Kiong Chen, Mark Rutherford, Yonghua Cong, David Chang. 475-478 [doi]