A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS - researchr publication

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Annachiara Spagnolo, Bob Verbruggen, Stefano D'Amico, Piet Wambacq. A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS. In ESSCIRC 2014 - 40th European Solid State Circuits Conference, Venice Lido, Italy, September 22-26, 2014. pages 75-78, IEEE, 2014. [doi]

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