Andreas Peter Burg - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 26 from 26

2022

Dynamic SCL Decoder With Path-Flipping for 5G Polar CodesYifei Shen, Alexios Balatsoukas-Stimming, Xiaohu You, Chuan Zhang 0001, Andreas Peter Burg. wcl, 11(2):391-395, 2022. [doi]

Fast Sequence Repetition Node-Based Successive Cancellation List Decoding for Polar CodesYifei Shen, Yuqing Ren, Andreas Toftegaard Kristensen, Alexios Balatsoukas-Stimming, Xiaohu You, Chuan Zhang 0001, Andreas Peter Burg. icc 2022: 116-122 [doi]

2016

Digital predistortion of power amplifier non-linearities for full-duplex transceiversAndrew Charles Mallory Austin, Alexios Balatsoukas-Stimming, Andreas Peter Burg. spawc 2016: 1-5 [doi]

Approximate computing for unreliable siliconAndreas Peter Burg. dtis 2016: 1 [doi]

Statistical fault injection for impact-evaluation of timing errors on application performanceJeremy Constantin, Andreas Peter Burg, Zheng Wang, Anupam Chattopadhyay, Georgios Karakonstantis. dac 2016: 13 [doi]

A multi-Gbps unrolled hardware list decoder for a systematic polar codePascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Andreas Peter Burg, Claude Thibeault, Warren J. Gross. acssc 2016: 1194-1198 [doi]

Hardware decoders for polar codes: An overviewPascal Giard, Gabi Sarkis, Alexios Balatsoukas-Stimming, YouZhe Fan, Chi-Ying Tsui, Andreas Peter Burg, Claude Thibeault, Warren J. Gross. iscas 2016: 149-152 [doi]

2015

On the statistical memory architecture exploration and optimizationCharalampos Antoniadis, Georgios Karakonstantis, Nestor E. Evmorfopoulos, Andreas Peter Burg, George I. Stamoulis. date 2015: 543-548 [doi]

Demo: Concurrent Spectrum Sensing and Transmission for Cognitive Radio using Self-Interference CancellationAndrew Charles Mallory Austin, Orion Afisiadis, Alexios Balatsoukas-Stimming, Andreas Peter Burg. mobihoc 2015: 407-408 [doi]

LLR-Based Successive Cancellation List Decoding of Polar CodesAlexios Balatsoukas-Stimming, Mani Bastani Parizi, Andreas Peter Burg. tsp, 63(19):5165-5179, 2015. [doi]

An Evolved GSM/EDGE Baseband ASIC Supporting Rx DiversityHarald Kröll, Stefan Zwicky, Benjamin Weber, Christoph Roth, David Tschopp, Christian Benkeser, Andreas Peter Burg, Qiuting Huang. jssc, 50(7):1690-1701, 2015. [doi]

Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoderPascal Andreas Meinerzhagen, Andrea Bonetti, Georgios Karakonstantis, Christoph Roth, Frank Giirkaynak, Andreas Peter Burg. iscas 2015: 1426-1429 [doi]

Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memoriesAdam Teman, Georgios Karakonstantis, Robert Giterman, Pascal Andreas Meinerzhagen, Andreas Peter Burg. date 2015: 489-494 [doi]

Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOIAdam Teman, Davide Rossi, Pascal Andreas Meinerzhagen, Luca Benini, Andreas Peter Burg. aspdac 2015: 81-86 [doi]

2014

2012

Two-port low-power gain-cell storage array: Voltage scaling and retention timeRashid Iqbal, Pascal Andreas Meinerzhagen, Andreas Peter Burg. iscas 2012: 2469-2472 [doi]

A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOSPascal Andreas Meinerzhagen, Oskar Andersson, Babak Mohammadi, S. M. Yasser Sherazi, Andreas Peter Burg, Joachim Neves Rodrigues. esscirc 2012: 321-324 [doi]

2011

A 772Mbit/s 8.81bit/nJ 90nm CMOS soft-input soft-output sphere decoderFilippo Borlenghi, Ernst Martin Witte, Gerd Ascheid, Heinrich Meyr, Andreas Peter Burg. asscc 2011: 297-300 [doi]

Random sampling ADC for sparse spectrum sensingPatrick Maechler, Norbert Felber, Andreas Peter Burg. eusipco 2011: 1200-1204 [doi]

T Domain in 65-nm CMOS TechnologyPascal Andreas Meinerzhagen, S. M. Yasser Sherazi, Andreas Peter Burg, Joachim Neves Rodrigues. esticas, 1(2):173-182, 2011. [doi]

Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systemsPascal Andreas Meinerzhagen, Onur Andiç, Jürg Treichler, Andreas Peter Burg. glvlsi 2011: 343-346 [doi]

Synthesis strategies for sub-VT systemsPascal Andreas Meinerzhagen, Oskar Andersson, S. M. Yasser Sherazi, Andreas Peter Burg, Joachim Neves Rodrigues. ecctd 2011: 552-555 [doi]

2006

VLSI implementation of pipelined sphere decoding with early terminationAndreas Peter Burg, Markus Wenk, Wolfgang Fichtner. eusipco 2006: 1-5 [doi]

2005

ASIC implementation of a MIMO-OFDM transceiver for 192 Mbps WLANsDavid Perels, Simon Haene, Peter Luethi, Andreas Peter Burg, Norbert Felber, Wolfgang Fichtner, Helmut Bölcskei. esscirc 2005: 215-218 [doi]

See Also

All Publications

Filter by Year
OR AND NOT 1

Filter by Type
OR AND NOT 1

Filter by Tag

Filter by Venue

[+]
OR AND NOT 1

Filter by Author

[+]
OR AND NOT 1

Filter by Top Terms

[+]
OR AND NOT 1

Researchr

Publications by 'Andreas Peter Burg'

Viewing Publication 1 - 26 from 26

2022

2016

2015

2014

2012

2011

2006

2005

See Also

All Publications

Filter by YearOR AND NOT 1

Filter by TypeOR AND NOT 1

Filter by Tag

Filter by Venue [+]OR AND NOT 1

Filter by Author [+]OR AND NOT 1

Filter by Top Terms [+]OR AND NOT 1

Researchr

Publications by 'Andreas Peter Burg'

Viewing Publication 1 - 26 from 26

2022

2016

2015

2014

2012

2011

2006

2005

Filter by Year
OR AND NOT 1

Filter by Type
OR AND NOT 1

Filter by Venue

[+]
OR AND NOT 1

Filter by Author

[+]
OR AND NOT 1

Filter by Top Terms

[+]
OR AND NOT 1