Abstract is missing.
- An arbiter based on-chip droop detector systemJinwook Jang, Wayne Burleson. 1-6 [doi]
- A programmable and scalable technique to design spintronic logic circuits based on magnetic tunnel junctionsShruti R. Patil, David J. Lilja. 7-12 [doi]
- Logic synthesis for integrated opticsChristopher Condrat, Priyank Kalla, Steve Blair. 13-18 [doi]
- Fine-grain reconfigurable logic cells based on double-gate CNTFETsKotb Jabeur, Nataliya Yakymets, Ian O Connor, Sébastien Le Beux. 19-24 [doi]
- RAMA: a self-assembled multiferroic magnetic QCA for low power systemsMehdi Kabir, Mircea R. Stan, Stuart A. Wolf, Ryan B. Comes, Jiwei Lu. 25-30 [doi]
- VISION: a framework for voltage island aware synthesis of interconnection networks-on-chipNishit Ashok Kapadia, Sudeep Pasricha. 31-36 [doi]
- Rover: routing on via-configurable fabrics for standard-cell-like structured ASICsLiang-Chi Lai, Hsih-Hang Chang, Rung-Bin Lin. 37-42 [doi]
- Run-time energy management of manycore systems through reconfigurable interconnectsJie Meng, Chao Chen, Ayse Kivilcim Coskun, Ajay Joshi. 43-48 [doi]
- Congestion and track usage improvement of large FPGAs using metro-on-FPGA methodologyMehdi Alipour, Mohammad Haji Seyed Javadi, Ali Jahanian. 49-54 [doi]
- Multi-objective topology synthesis and FPGA prototyping framework of application specific network-on-chipXinyu Li, Omar Hammami. 55-60 [doi]
- Efficient shift-adds design of digit-serial multiple constant multiplicationsLevent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José C. Monteiro. 61-66 [doi]
- Accelerating Itoh-Tsujii multiplicative inversion algorithm for FPGAsSujoy Sinha Roy, Chester Rebeiro, Debdeep Mukhopadhyay. 67-72 [doi]
- FPGA implementation of binary edwards curve usingternary representationAyantika Chatterjee, Indranil Sengupta. 73-78 [doi]
- Design of low-power multiple constant multiplications using low-complexity minimum depth operationsLevent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro. 79-84 [doi]
- High performance technique for database applicationsusing a hybrid GPU/CPU platformM. Affan Zidan, Talal Bonny, Khaled N. Salama. 85-90 [doi]
- Design and management of 3D-stacked NUCA cache for chip multiprocessorsJongpil Jung, Kyungsu Kang, Chong-Min Kyung. 91-96 [doi]
- Design techniques to improve the device write margin for MRAM-based cache memoryHongbin Sun, Chuanyin Liu, Nanning Zheng, Tai Min, Tong Zhang. 97-102 [doi]
- DRAM energy reduction by prefetching-based memory traffic clusteringYebin Lee, Soontae Kim. 103-108 [doi]
- A low-power TCAM design using mask-aware match-line (MAML) techniqueYen-Jen Chang, Tung-Chi Wu. 109-114 [doi]
- Hardware-assisted dynamic power and thermal management in multi-core SoCsGeorge Kornaros, Dionisios N. Pnevmatikatos. 115-120 [doi]
- A 7T SRAM bit-cell for low-power embedded memoriesWasim Hussain, Shah M. Jahinuzzaman. 121-126 [doi]
- A static-switching pulse domino technique for statistical power reduction of wide fan-in dynamic gatesRahul Singh, Jae Cheol Son, Ukrae Cho, Gunok Jung, Min-Su Kim, Hyoungwook Lee, Suhwan Kim. 127-132 [doi]
- A 45.6μ:::2::: 13.4μw 7.1v/v resolution sub-threshold based digital process-sensing circuit in 45nm CMOSBasab Datta, Wayne Burleson. 133-138 [doi]
- A new balanced 4-moduli set {2:::::::k:::::::, 2:::::::n::::::: - 1, 2:::::::n::::::: + 1, 2:::::::n+1:::::::-1} and its reverse converter design for efficient fir filter implementationGayathri Chalivendra, Vinay Hanumaiah, Sarma B. K. Vrudhula. 139-144 [doi]
- Towards robust nano-CMOS sense amplifier design: a dual-threshold versus dual-oxide perspectiveOghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos, Mahesh Poolakkaparambil. 145-150 [doi]
- A design methodology for the automatic sizing of standard-cell librariesChristian Pilato, Fabrizio Ferrandi, Davide Pandini. 151-156 [doi]
- Integration of behavioral synthesis and floorplanning for asynchronous circuits with bundled-data implementationNaohiro Hamada, Hiroshi Saito. 157-162 [doi]
- Coupling latency-insensitivity with variable-latency for better than worst case design: a RISC case studyMario R. Casu, Stefano Colazzo, Paolo Mantovani. 163-168 [doi]
- Reconfigurable controllers for synchronization via waggingJames Sebastian Guido, Alexandre Yakovlev. 175-180 [doi]
- Variation-immune quasi delay-insensitive implementation on nano-crossbar arraysMasoud Zamani, Mehdi Baradaran Tahoori. 181-186 [doi]
- An efficient algorithm for custom instruction enumerationChenglong Xiao, Emmanuel Casseau. 187-192 [doi]
- An approximation algorithm for cofactoring-based synthesisAnna Bernasconi, Valentina Ciriani, Valentino Liberali, Gabriella Trucco, Tiziano Villa. 193-198 [doi]
- Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimizationFeifei Niu, Qiang Zhou, Hailong Yao, Yici Cai, Jianlei Yang, Chin-Ngai Sze. 199-204 [doi]
- New optimal layer assignment for bus-oriented escape routingJin-Tai Yan, Zhi-Wei Chen. 205-210 [doi]
- Acceleration of random-walk-based linear circuit analysis using importance samplingTetsuro Miyakawa, Koh Yamanaga, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato. 211-216 [doi]
- A 65 nm CMOS low power RF front-end for L1/E1 GPS/Galileo signalsGaetano Rivela, Pietro Scavini, Daniele Grasso, Antonino Calcagno, Maria Gabriella Castro, Giuseppe Di Chiara, Giuseppe Avellone, Giovanni Cali , Salvatore Scaccianoce. 217-222 [doi]
- Simulation-based equivalence checking between SystemC models at different levels of abstractionDaniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler. 223-228 [doi]
- Fast high-performance algorithms for multi-pin droplet routing in digital microfluidic biochipsPranab Roy, Hafizur Rahaman, Parthasarathi Dasgupta. 229-234 [doi]
- A countermeasure against power analysis attacks for FSR-based stream ciphersShohreh Sharif Mansouri, Elena Dubrova. 235-240 [doi]
- Low jitter audio range PLL with ultra low power dissipationFu Luo, Godi Fischer. 241-246 [doi]
- Layout-aware variation evaluation of analog circuits and its validity on op-amp designsKota Shinohara, Mihoko Hidaka, Jing Li, Qing Dong, Bo Yang, Shigetoshi Nakatake. 247-252 [doi]
- A linear programming approach for minimum NBTI vector selectionFarshad Firouzi, Saman Kiamehr, Mehdi Baradaran Tahoori. 253-258 [doi]
- Fitting standard cell performance to generalized Lambda distributionsAndré Lange, Joachim Haase, Hendrik T. Mau. 259-264 [doi]
- Stress aware switching activity driven low power design of critical paths in nanoscale CMOS circuitsSudarshan Srinivasan, Bharath Phanibhushana, Arunkumar Vijayakumar, Sandip Kundu. 265-270 [doi]
- Simultaneous variation-aware architecture exploration and task scheduling for MPSoC energy minimizationMahmoud Momtazpour, Mahboobeh Ghorbani, Maziar Goudarzi, Esmaeil Sanaei. 271-276 [doi]
- Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cellsNivard Aymerich, Shrikanth Ganapathy, Antonio Rubio, Ramon Canal, Antonio González. 277-282 [doi]
- Redundancy in SAR ADCsAlbert H. Chang, Hae-Seung Lee, Duane S. Boning. 283-288 [doi]
- A high sensitivity and process tolerant digital thermal sensing scheme for 3-D IcsBasab Datta, Wayne Burleson. 289-294 [doi]
- Buffering of frequent accesses for reduced cache agingAndrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino. 295-300 [doi]
- Combined architecture and hardening techniques exploration for reliable embedded system designCristiana Bolchini, Antonio Miele, Christian Pilato. 301-306 [doi]
- Ordered coloring-based resource binding for datapaths with improved skew-adjustabilityMineo Kaneko, Keisuke Inoue. 307-312 [doi]
- Power estimation of dividers implemented in FPGAsRuzica Jevtic, Bojan Jovanovic, Carlos Carreras. 313-318 [doi]
- Nanometer-scale standard cell library for enhanced redundant via1 insertion rateTsang-Chi Kan, Shih Hsien Yang, Ting-Feng Chang, Shanq-Jang Ruan. 319-324 [doi]
- Circuit design of a dual-versioning L1 data cache for optimistic concurrencyAzam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero. 325-330 [doi]
- Real-time address trace compression for emulated and real system-on-chip processor core debuggingBojan Mihajlovic, Zeljko Zilic. 331-336 [doi]
- Investigating modern layout representations for improved 3d design automationRobert Fischbach, Jens Lienig, Johann Knechtel. 337-342 [doi]
- Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systemsPascal Andreas Meinerzhagen, Onur Andiç, Jürg Treichler, Andreas Peter Burg. 343-346 [doi]
- Power efficient partial product compressionChiu-wei Pan, Zhao Wang, Yuanchen Song, Carl Sechen. 347-350 [doi]
- Evaluation of FPGA routing architectures under process variationFatemeh Sadat Pourhashemi, Morteza Saheb Zamani. 351-354 [doi]
- High resolution MASH 2-2 Sigma Delta interface for capacitive accelerometersSwathi Ramasahayam, Satyam Mandavilli. 355-358 [doi]
- Influence of metallic tubes on the reliability of CNTFET SRAMs: error mechanisms and countermeasuresZhen Wang, Mark G. Karpovsky, Ajay Joshi. 359-362 [doi]
- A new low power and area efficient semi-digital PLL architecture for low bandwidth applicationsMarkus Dietl, Puneet Sareen. 363-366 [doi]
- SIAR: splitting-graph-based interactive analog routerFan Yang, Hailong Yao, Qiang Zhou, Yici Cai. 367-370 [doi]
- A comparative study of state-of-the-art low-power CAM match-line sense amplifier designsAnh-Tuan Do, Xiaoliang Tan, Shoushun Chen, Zhi-Hui Kong, Kiat Seng Yeo. 371-374 [doi]
- Sensitivity of neuromorphic circuits using nanoelectronic resistive switches to pulse synchronizationArne Heittmann, Tobias G. Noll. 375-378 [doi]
- A dual-core system solution for wearable health monitorsFrank Bouwens, Jos Huisken, Harmke de Groot, Martijn Bennebroek, Anteneh A. Abbo, Octavio Santana, Jef L. van Meerbergen, Antoine Fraboulet. 379-382 [doi]
- Robust signaling techniques for through silicon via bundlesKrishna C. Chillara, Jinwook Jang, Wayne P. Burleson. 383-386 [doi]
- Efficient realization of RTD-CMOS logic gatesJuan Núñez, Maria J. Avedillo, José M. Quintana. 387-390 [doi]
- On residue removal in digital microfluidic biochipsDebasis Mitra, Sarmishtha Ghoshal, Hafizur Rahaman, Krishnendu Chakrabarty, Bhargab B. Bhattacharya. 391-394 [doi]
- Repeater insertion in power-managed VLSI systemsHouman Zarrabi, Asim J. Al-Khalili, Yvon Savaria. 395-398 [doi]
- Experimental demonstration of standby power reduction using voltage stacking in an 8Kb embedded FDSOI SRAMAdam C. Cabe, Mircea R. Stan. 399-402 [doi]
- Handling intra-die variations in PSTALuís Guerra e Silva, Luis Miguel Silveira. 403-406 [doi]
- Integrated logic synthesis using simulated annealingPetra Färm, Elena Dubrova, Andreas Kuehlmann. 407-410 [doi]
- A geometric programming aided knowledge based approach for analog circuit synthesis and sizingSupriyo Maji, Pradip Mandal. 411-414 [doi]
- Analyzing throughput of power and thermal-constraint multicore processor under NBTI effectShi-Qun Zheng, Ing-Chao Lin, Yen-Han Lee. 415-418 [doi]
- Efficient method to compute minimum decision chains of Boolean functionsMayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis. 419-422 [doi]
- Time-mode reconstruction iir filters for ΣΔ phase modulation applicationsAli Ameri, Gordon W. Roberts. 423-426 [doi]
- SMECY: smart multi-core embedded systemsFrançois Pacull, Koen Bertels, Martin Danek, Giulio Urlini. 427-428 [doi]
- Magnetic memory (MRAM), a new area for 2D and 3D SoC/SiP designLionel Torres, Weisheng Zhao. 429-430 [doi]
- Design of MRAM based logic circuits and its applicationsWeisheng Zhao, Lionel Torres, Yoann Guillemenet, Luis Vitório Cargnini, Yahya Lakys, Jacques-Olivier Klein, Dafine Ravelosona, Gilles Sassatelli, Claude Chappert. 431-436 [doi]
- Instant power-on nonvolatile FPGA based on MTJ/MOS-hybrid circuitryTakahiro Hanyu. 437-438 [doi]
- Enabling architectural innovations using non-volatile memoryVijaykrishnan Narayanan, Vinay Saripalli, Karthik Swaminathan, Ravindhiran Mukundrajan, Guangyu Sun, Yuan Xie, Suman Datta. 439-444 [doi]
- Challenges for non-volatile memory & logic manufacturing utilizing magnetic tunnel junction on 300 mm waferKeizo Kinoshita. 445-446 [doi]
- Hardware security in VLSIWayne Burleson, Yusuf Leblebici. 447-448 [doi]
- Integrated circuits metering for piracy protection and digital rights management: an overviewFarinaz Koushanfar. 449-454 [doi]
- Physically unclonable functions: manufacturing variability as an unclonable device identifierIngrid Verbauwhede, Roel Maes. 455-460 [doi]
- The future of high-speed cryptography: new computing platforms and new ciphersTim Güneysu, Stefan Heyse, Christof Paar. 461-466 [doi]
- Quantum devices and optical computing: introductionBraulio García-Cámara. 467-468 [doi]
- Optically leviting dielectrics in the quantum regimeOriol Romero-Isart, Anika C. Panzer, J. Ignacio Cirac. 469-470 [doi]
- Solid state optical quantum memoriesHugues de Riedmatten. 473-474 [doi]
- Deeply-scaled CMOS-integrated nanophotonic devices for next generation supercomputersSolomon Assefa, Wiliam M. J. Green, Alexander Rylyakov, Clint Schow, Folker Horst, Yurü A. Vlasov. 475-476 [doi]