Paulo F. Flores - researchr alias

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Viewing Publication 1 - 67 from 67

2023

Compact CMOS-Compatible Majority Gate Using Body Biasing in FDSOI TechnologyBrunno Alves de Abreu, Albi Mema, Simon Thomann, Guilherme Paim, Paulo F. Flores, Sergio Bampi, Hussam Amrouch. esticas, 13(1):86-95, March 2023. [doi]

Architectural Exploration for Energy-Efficient LMS and NLMS Adaptive Filters VLSI DesignPedro Tauã Lopes Pereira, Guilherme Paim, Eduardo A. C. da Costa, Paulo F. Flores, Sergio Bampi. newcas 2023: 1-5 [doi]

AxASRE: A Novel Approach to Approximate Adder Synthesis Results EstimationPedro Tauã Lopes Pereira, Guilherme Paim, Paulo F. Flores, Eduardo A. C. da Costa, Sergio Bampi. dsn 2023: 183-186 [doi]

2020

r recoding with common subexpression elimination for multiple constant multiplicationAhmed Liacha, Abdelkrim Kamel Oudjida, Mohammed Bakiri, José Monteiro, Paulo F. Flores. iet-cds, 14(7):990-994, 2020. [doi]

2016

A novel method for the approximation of multiplierless constant matrix vector multiplicationLevent Aksoy, Paulo F. Flores, José Monteiro. ejes, 2016:12, 2016. [doi]

2015

Exact and Approximate Algorithms for the Filter Design Optimization ProblemLevent Aksoy, Paulo F. Flores, José C. Monteiro. tsp, 63(1):142-154, 2015. [doi]

Approximation of multiple constant multiplications using minimum look-up tables on FPGALevent Aksoy, Paulo F. Flores, José C. Monteiro. iscas 2015: 2884-2887 [doi]

A Novel Method for the Approximation of Multiplierless Constant Matrix Vector MultiplicationLevent Aksoy, Paulo F. Flores, José C. Monteiro. euc 2015: 98-105 [doi]

Quaternary Logic Lookup Table in Standard CMOSDiogo Brito, Taimur Gibran Rabuske, Jorge R. Fernandes, Paulo F. Flores, José C. Monteiro. tvlsi, 23(2):306-316, 2015. [doi]

Multicore SIMD ASIP for Next-Generation Sequencing and Alignment Biochip PlatformsNuno Neves, Nuno Sebastião, David Martins de Matos, Pedro Tomás, Paulo F. Flores, Nuno Roma. tvlsi, 23(7):1287-1300, 2015. [doi]

2014

Optimization of design complexity in time-multiplexed constant multiplicationsLevent Aksoy, Paulo F. Flores, José C. Monteiro. date 2014: 1-4 [doi]

ECHO: A novel method for the multiplierless design of constant array vector multiplicationLevent Aksoy, Paulo F. Flores, José C. Monteiro. iscas 2014: 1456-1459 [doi]

Efficient design of FIR filters using hybrid multiple constant multiplications on FPGALevent Aksoy, Paulo F. Flores, José C. Monteiro. iccd 2014: 42-47 [doi]

Multiplierless Design of Folded DSP BlocksLevent Aksoy, Paulo F. Flores, José C. Monteiro. todaes, 20(1):14, 2014. [doi]

A Tutorial on Multiplierless Design of FIR Filters: Algorithms and ArchitecturesLevent Aksoy, Paulo F. Flores, José Monteiro. cssp, 33(6):1689-1719, 2014. [doi]

Optimized ASIP architecture for compressed BWT-indexed search in bioinformatics applicationsNuno Sebastião, Paulo F. Flores, Nuno Roma. hpcs 2014: 527-534 [doi]

2013

Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD ToolLevent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José Monteiro. tvlsi, 21(3):498-511, 2013. [doi]

SIREN: a depth-first search algorithm for the filter design optimization problemLevent Aksoy, Paulo F. Flores, José Monteiro. glvlsi 2013: 179-184 [doi]

Exploration of tradeoffs in the design of integer cosine transforms for image compressionLevent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro. ecctd 2013: 1-4 [doi]

Towards the least complex time-multiplexed constant multiplicationLevent Aksoy, Paulo F. Flores, José C. Monteiro. vlsi 2013: 328-331 [doi]

Standard CMOS voltage-mode QLUT using a clock boosting techniqueDiogo Brito, Jorge R. Fernandes, Paulo F. Flores, José C. Monteiro. newcas 2013: 1-4 [doi]

Improving SAT Solver Efficiency Using a Multi-Core ApproachRicardo Marques, Luis G. Silva, Paulo F. Flores, L. Miguel Silveira. flairs 2013: [doi]

BioBlaze: Multi-core SIMD ASIP for DNA sequence alignmentNuno Neves, Nuno Sebastião, Andre Patricio, David Matos, Pedro Tomás, Paulo F. Flores, Nuno Roma. asap 2013: 241-244 [doi]

Configurable and scalable class of high performance hardware accelerators for simultaneous DNA sequence alignmentNuno Sebastião, Nuno Roma, Paulo F. Flores. concurrency, 25(10):1319-1339, 2013. [doi]

2012

High-level algorithms for the optimization of gate-level area in digit-serial multiple constant multiplicationsLevent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José Monteiro. integration, 45(3):294-306, 2012. [doi]

Multiple tunable constant multiplications: Algorithms and applicationsLevent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro. iccad 2012: 473-479 [doi]

Design of low-complexity digital finite impulse response filters on FPGAsLevent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro. date 2012: 1197-1202 [doi]

Optimization Algorithms for the Multiplierless Realization of Linear TransformsLevent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro. todaes, 17(1):3, 2012. [doi]

Design and characterization of a QLUT in a standard CMOS processDiogo Brito, Jorge Fernandes, Paulo F. Flores, José C. Monteiro. icecsys 2012: 288-291 [doi]

Integrated Hardware Architecture for Efficient Computation of the $n$-Best Bio-Sequence Local Alignments in Embedded PlatformsNuno Sebastião, Nuno Roma, Paulo F. Flores. tvlsi, 20(7):1262-1275, 2012. [doi]

Hardware accelerator architecture for simultaneous short-read DNA sequences alignment with enhanced traceback phaseNuno Sebastião, Nuno Roma, Paulo F. Flores. mam, 36(2):96-109, 2012. [doi]

2011

Optimization of area in digit-serial Multiple Constant Multiplications at gate-levelLevent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José C. Monteiro. iscas 2011: 2737-2740 [doi]

Efficient shift-adds design of digit-serial multiple constant multiplicationsLevent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José C. Monteiro. glvlsi 2011: 61-66 [doi]

Design of low-power multiple constant multiplications using low-complexity minimum depth operationsLevent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro. glvlsi 2011: 79-84 [doi]

Finding the optimal tradeoff between area and delay in multiple constant multiplicationsLevent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro. mam, 35(8):729-741, 2011. [doi]

Optimization of gate-level area in high throughput Multiple Constant MultiplicationsLevent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro. ecctd 2011: 588-591 [doi]

A hybrid algorithm for the optimization of area and delay in linear DSP transformsLevent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro. vlsi 2011: 148-153 [doi]

Multiplierless Design of Linear DSP TransformsLevent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro. vlsi 2012: 73-93 [doi]

Low Power Multiple-Value Voltage-Mode Look-Up Table for Quaternary Field Programmable Gate ArraysCristiano Lazzari, Jorge Fernandes, Paulo F. Flores, José Monteiro. jolpe, 7(2):294-301, 2011. [doi]

2010

Optimization of Area and Delay at Gate-Level in Multiple Constant MultiplicationsLevent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro. dsd 2010: 3-10 [doi]

Search algorithms for the multiple constant multiplications problem: Exact and approximateLevent Aksoy, Ece Olcay Günes, Paulo F. Flores. mam, 34(5):151-162, 2010. [doi]

Design of low-complexity and high-speed digital Finite Impulse Response filtersDiego Jaccottet, Eduardo Costa, Levent Aksoy, Paulo F. Flores, Josee Monteiro. vlsi 2010: 292-297 [doi]

An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAsCristiano Lazzari, Jorge Fernandes, Paulo F. Flores, José C. Monteiro. patmos 2011: 84-93 [doi]

A new quaternary FPGA based on a voltage-mode multi-valued circuitCristiano Lazzari, Paulo F. Flores, José Monteiro, Luigi Carro. date 2010: 1797-1802 [doi]

Voltage-mode quaternary FPGAs: An evaluation of interconnectionsCristiano Lazzari, Paulo F. Flores, José Monteiro, Luigi Carro. iscas 2010: 869-872 [doi]

Integrated accelerator architecture for DNA sequences alignment with enhanced traceback phaseNuno Sebastiao, Tiago Dias, Nuno Roma, Paulo F. Flores. ieeehpcs 2010: 16-23 [doi]

2009

PMSat: a parallel version of MiniSATLuís Gil, Paulo F. Flores, Luis Miguel Silveira. jsat, 6(1-3):71-98, 2009. [doi]

Generating realistic stimuli for accurate power grid analysisPedro Marques Morgado, Paulo F. Flores, L. Miguel Silveira. todaes, 14(3), 2009. [doi]

2008

2007

2006

2005

Maximal sharing of partial terms in MCM under minimal signed digit representationEduardo A. C. da Costa, Paulo F. Flores, José Monteiro. ecctd 2005: 221-224 [doi]

An exact algorithm for the maximal sharing of partial terms in multiple constant multiplicationsPaulo F. Flores, José C. Monteiro, Eduardo A. C. da Costa. iccad 2005: 13-16

2001

An exact solution to the minimum size test pattern problemPaulo F. Flores, Horácio C. Neto, João P. Marques Silva. todaes, 6(4):629-644, 2001. [doi]

1999

1998

An exact solution to the minimum size test pattern problemPaulo F. Flores, Horácio C. Neto, João P. Marques Silva. In ICCD. 1998: 510-515 [doi]

1997

Prime Implicant Computation Using Satisfiability AlgorithmsVasco M. Manquinho, Paulo F. Flores, João P. Marques Silva, Arlindo L. Oliveira. ictai 1997: 232-239 [doi]

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