- Tiago Almeida, Isaías B. Felzmann, Lucas Francisco Wanner. A heuristic approach for near Pareto-optimal design space exploration in Approximate High-Level Synthesis. Integration, 108:102638, 2026.
- Jun-Da Chen, Liang-Chung Shen. An S to Ku band wideband low-voltage low-power up-conversion mixer in 0.18-μm CMOS technology. Integration, 106:102536, 2026.
- Ritu Ranjan, Sanjoy Mandal. Design of electronic system for linearization of sinusoidal characteristics of cascaded tunneling magneto-resistance sensor. Integration, 106:102540, 2026.
- Shyamosree Goswami, Adwait Wakankar, Partha Bhattacharyya, Anup Dandapat. Achieving superior segmented CAM efficiency with pre-charge free local search based hybrid matcher for high speed applications. Integration, 107:102621, 2026.
- Zhikui Duan, Dayi Yang, Shaobo He, Xinmei Yu, Zhuorui Tang, Qingyu Wu. A CMOS circuit for ultra high frequency chaos generation utilizing a Clapp oscillator with dual memristors. Integration, 106:102601, 2026.
- Manhong Fan, Qingsong Liu, Shiqi Xu, Yonglong Bai. Dynamics analysis and application of multi-stable Hopfield neural networks under pulsed current stimulation. Integration, 107:102632, 2026.
- Djaballah Merouane, Ayat Louiza, Rabah Ouchikh, Azzaz Mohammed Salah. High-performance OTFS transmitter on FPGA: A hybrid HLS/VHDL design. Integration, 106:102542, 2026.
- Qiyao He, Zhang Hu, Yinshui Xia, Lunyao Wang, Zhufei Chu. Enhancing logic optimization of Alliance tool based on directed acyclic graphs. Integration, 106:102580, 2026.
- Yuanfa Ji, Haihui Zhang, Xiyan Sun, Furong Jiang, Qiang Fu. A test data compression method based on sliding-window encoding and matching length reuse. Integration, 108:102663, 2026.
- Vasundhara Trivedi, Harman Singh Bagga, Gopal Raut, Santosh Kumar Vishvakarma. Adaptive-precision SIMD architecture for high-throughput and resource-efficient DNN acceleration. Integration, 108:102666, 2026.