- Anirban Bhattacharjee, Chandan Bandyopadhyay, Philipp Niemann 0001, Bappaditya Mondal, Rolf Drechsler, Hafizur Rahaman 0001. An improved heuristic technique for nearest neighbor realization of quantum circuits in 2D architecture. Integration, 76:40-54, 2021.
- Seyed Hosein Attarzadeh Niaki, Ingo Sander, Mohammad Ahmadi. An automated parallel simulation flow for cyber-physical system design. Integration, 77:48-58, 2021.
- Young Seo Lee, Kyung Min Kim, Ji-Heon Lee, Young-Ho Gong, Seon Wook Kim, Sung Woo Chung. Monolithic 3D stacked multiply-accumulate units. Integration, 76:183-189, 2021.
- Zhaohui Chen, Yuan Ma, Tianyu Chen, Jingqiang Lin, Jiwu Jing. High-performance area-efficient polynomial ring processor for CRYSTALS-Kyber on FPGAs. Integration, 78:25-35, 2021.
- Anas Razzaq, Sajjad Rostami-Sani, Andy Gean Ye. Designing efficient FPGA tiles for power-constrained ultra-low-power applications. Integration, 78:124-134, 2021.
- Haoyu Yang, Wei Zhong, Yuzhe Ma, Hao Geng, Ran Chen, Wanli Chen, Bei Yu 0001. VLSI mask optimization: From shallow to deep learning. Integration, 77:96-103, 2021.
- Bahram Rashidi. Compact and efficient structure of 8-bit S-box for lightweight cryptography. Integration, 76:172-182, 2021.
- Srinivas Katkoori, Sheikh Ariful Islam, Sujana Kakarla. Partial evaluation based triple modular redundancy for single event upset mitigation. Integration, 77:167-179, 2021.
- Han Zhou, Liang Chen, Sheldon X.-D. Tan. Robust power grid network design considering EM aging effects for multi-segment wires. Integration, 77:38-47, 2021.
- Shuo Li, Junren Pan, Jin He 0002, Zhiyuan Cao, Hao Wang 0046, Sheng Chang, Qijun Huang. A 25-Gb/s inductorless SiGe BiCMOS receiver for 100-Gb/s optical links. Integration, 77:131-138, 2021.