- Jun-Da Chen, Liang-Chung Shen. An S to Ku band wideband low-voltage low-power up-conversion mixer in 0.18-μm CMOS technology. Integration, 106:102536, 2026.
- Ritu Ranjan, Sanjoy Mandal. Design of electronic system for linearization of sinusoidal characteristics of cascaded tunneling magneto-resistance sensor. Integration, 106:102540, 2026.
- Djaballah Merouane, Ayat Louiza, Rabah Ouchikh, Azzaz Mohammed Salah. High-performance OTFS transmitter on FPGA: A hybrid HLS/VHDL design. Integration, 106:102542, 2026.
- Qiyao He, Zhang Hu, Yinshui Xia, Lunyao Wang, Zhufei Chu. Enhancing logic optimization of Alliance tool based on directed acyclic graphs. Integration, 106:102580, 2026.
- Anish Paul, Siya Sharma, Kulbhushan Sharma. Design of a soft error resilient 13T SRAM architecture for radiation-prone environments in FinFET 18 nm technology. Integration, 106:102574, 2026.
- Chenkai Zhang, Huibin Wang, Yiyan Zhang, Chunyan Ma. Dynamics analysis of 3D hyperchaotic map based on discrete Hopfield neural network coupled discrete cosine memristor. Integration, 106:102579, 2026.
- Meeniga Srikanth Reddy, Debanjali Nath, Debajit Deb. Power Gated-SRAM and novel header-footer multiplexer based ultra low power Look-Up Table design. Integration, 106:102566, 2026.
- Ramzi Ayadi, Med Lassaad Kaddachi, Yassine Bouteraa. Hybrid GACO approach for optimized floorplanning in partially reconfigurable FPGAs. Integration, 106:102578, 2026.
- Oumayma Bel Haj Salah, Seifeddine Messaoud, Mohamed Ali Hajjaji, Mohamed Atri, Noureddine Liouane. Low-latency QYOLOv10-based FPGA implementation for real-time object detection. Integration, 106:102591, 2026.
- Nitish Kumar, Aakif Nehal, Aditya Vikram Singh, Kavindra Kandpal, Manish Goswami. Efficient, reliable, and secure PUF architecture with temperature invariance and ML attack resilience. Integration, 106:102538, 2026.