Table of Contents

• Online fault detection and tolerance for photovoltaic energy harvesting systemsXue Lin, Yanzhi Wang, Di Zhu, Naehyuck Chang, Massoud Pedram. 1-6 [doi]
• Tunable sensors for process-aware voltage scalingTuck Boon Chan, Andrew B. Kahng. 7-14 [doi]
• Collaborative calibration of on-chip thermal sensors using performance countersShiting (Justin) Lu, Russell Tessier, Wayne Burleson. 15-22 [doi]
• Spatial correlation modeling for probe test cost reduction in RF devicesNathan Kupp, Ke Huang, John M. Carulli Jr., Yiorgos Makris. 23-29 [doi]
• Small-delay-fault ATPG with waveform accuracyMatthias Sauer, Alexander Czutro, Ilia Polian, Bernd Becker. 30-36 [doi]
• Experimental analysis of a ring oscillator network for hardware Trojan detection in a 90nm ASICAndrew Ferraiuolo, Xuehui Zhang, Mohammad Tehranipoor. 37-42 [doi]
• Layout small-angle rotation and shift for EUV defect mitigationHongbo Zhang, Yuelin Du, Martin D. F. Wong, Yunfei Deng, Pawitter Mangat. 43-49 [doi]
• A methodology for the early exploration of design rules for multiple-patterning technologiesRani S. Ghaida, Tanaya Sahu, Parag Kulkarni, Puneet Gupta. 50-56 [doi]
• A polynomial time triple patterning algorithm for cell based row-structure layoutHaitong Tian, Hongbo Zhang, Qiang Ma 0002, Zigang Xiao, Martin D. F. Wong. 57-64 [doi]
• Improving last level cache locality by integrating loop and data transformationsWei Ding, Mahmut T. Kandemir. 65-72 [doi]
• Asymmetric DRAM synthesis for heterogeneous chip multiprocessors in 3D-stacked architectureMinje Jun, Myoung Jin Kim, Eui-Young Chung. 73-80 [doi]
• Optimizing bandwidth and power of graphics memory with hybrid memory technologies and adaptive data migrationJishen Zhao, Yuan Xie. 81-87 [doi]
• Probabilistic design methodology to improve run-time stability and performance of STT-RAM cachesXiuyuan Bi, Zhenyu Sun, Hai Li, Wenqing Wu. 88-94 [doi]
• Bridging pre- and post-silicon debugging with BiPeDAndrew DeOrio, Jialin Li, Valeria Bertacco. 95-100 [doi]
• Novel test detection to improve simulation efficiency - A commercial experimentWen Chen, Nik Sumikawa, Li-C. Wang, Jayanta Bhadra, Xiushan Feng, Magdy S. Abadir. 101-108 [doi]
• A robust general constrained random pattern generator for constraints with variable orderingBo-Han Wu, Chung-Yang (Ric) Huang. 109-114 [doi]
• Fast and scalable hybrid functional verification and debug with dynamically reconfigurable co-simulationSomnath Banerjee, Tushar Gupta. 115-122 [doi]
• TRIAD: A triple patterning lithography aware detailed routerYen-Hung Lin, Bei Yu, David Z. Pan, Yih-Lang Li. 123-129 [doi]
• Maze routing algorithms with exact matching constraints for analog and mixed signal designsMuhammet Mustafa Ozdal, Renato Fernandes Hentschke. 130-136 [doi]
• Reclaiming over-the-IP-block routing resources with buffering-aware rectilinear Steiner minimum tree constructionYilin Zhang, Ashutosh Chakraborty, Salim Chowdhury, David Z. Pan. 137-143 [doi]
• Construction of rectilinear Steiner minimum trees with slew constraints over obstaclesTao Huang, Evangeline F. Y. Young. 144-151 [doi]
• Noise based logic: Why noise?He Wen, Laszlo B. Kish. 152-155 [doi]
• An efficient implementation of numerical integration using logical computation on stochastic bit streamsWeikang Qian, Chen Wang, Peng Li, David J. Lilja, Kia Bazargan, Marc D. Riedel. 156-162 [doi]
• Utilizing random noise in cryptography: Where is the Tofu?Hui Geng, Jun Wu, Jianming Liu, Minsu Choi, Yiyu Shi. 163-167 [doi]
• Learning from biological neurons to compute with electronic noise specialHsin Chen, Chih-Cheng Lu, Yi-Da Wu, Tang-Jung Chiu. 168-171 [doi]
• On the computation of criticality in statistical timing analysisS. Ramprasath, V. Vasudevan. 172-179 [doi]
• A dynamic method for efficient random mismatch characterization of standard cellsWangyang Zhang, Amith Singhee, Jinjun Xiong, Peter A. Habitz, Amol Joshi, Chandu Visweswariah, James Sundquist. 180-186 [doi]
• Classifying circuit performance using active-learning guided support vector machinesHonghuang Lin, Peng Li. 187-194 [doi]
• Scalable sampling methodology for logic simulation: Reduced-Ordered Monte CarloChien-Chih Yu, Armin Alaghi, John P. Hayes. 195-201 [doi]
• Trajectory-Directed discrete state space modeling for formal verification of nonlinear analog circuitsSebastian Steinhorst, Lars Hedrich. 202-209 [doi]
• Word level feature discovery to enhance quality of assertion miningLingyi Liu, Chen-Hsuan Lin, Shobha Vasudevan. 210-217 [doi]
• Impact of range and precision in technology on cell-based designJohn Lee, Puneet Gupta. 218-225 [doi]
• An efficient algorithm for library-based cell-type selection in high-performance low-power designsLi Li 0021, Peng Kang, Yinghai Lu, Hai Zhou. 226-232 [doi]
• Sensitivity-guided metaheuristics for accurate discrete gate sizingJin Hu, Andrew B. Kahng, Seokhyeong Kang, Myung-Chul Kim, Igor L. Markov. 233-239 [doi]
• Dealing with IC manufacturability in extreme scaling (Embedded tutorial paper)Bei Yu, Jhih-Rong Gao, Duo Ding, Yongchan Ban, Jae-Seok Yang, Kun Yuan, Minsik Cho, David Z. Pan. 240-242 [doi]
• Circuit reliability: From Physics to Architectures: Embedded tutorial paperJianxin Fang, Saket Gupta, Sanjay V. Kumar, Sravan K. Marella, Vivek Mishra, Pingqiang Zhou, Sachin S. Sapatnekar. 243-246 [doi]
• Stability assurance and design optimization of large power delivery networks with multiple on-chip voltage regulatorsSuming Lai, Boyuan Yan, Peng Li. 247-254 [doi]
• A silicon-validated methodology for power delivery modeling and simulationCheng Zhuo, Gustavo R. Wilke, Ritochit Chakraborty, Alaeddin Aydiner, Sourav Chakravarty, Wei-Kai Shih. 255-262 [doi]
• Optimization of on-chip switched-capacitor DC-DC converters for high-performance applicationsPingqiang Zhou, Won Ho Choi, Bongjin Kim, Chris H. Kim, Sachin S. Sapatnekar. 263-270 [doi]
• Scaling the "Memory Wall": Designer trackShih-Lien Lu, Tanay Karnik, Ganapati Srinivasa, Kai-Yuan Chao, Doug Carmean, Jim Held. 271-272 [doi]
• Test challenges in designing complex 3D chips: What in on the horizon for EDA industry?: Designer trackSandeep Kumar Goel. 273 [doi]
• 3D integrated circuits: Designing in a new dimension: Designer trackRobert Patti. 274 [doi]
• Progress and challenges in VLSI placement researchIgor L. Markov, Jin Hu, Myung-Chul Kim. 275-282 [doi]
• Placement: Hot or Not?Charles J. Alpert, Zhuo Li, Gi-Joon Nam, Chin-Ngai Sze, Natarajan Viswanathan, Samuel I. Ward. 283-290 [doi]
• Modeling and design automation of biological circuits and systemsNatasa Miskov-Zivanov, James R. Faeder, Chris J. Myers, Herbert M. Sauro. 291-293 [doi]
• CACTI-IO: CACTI with off-chip power-area-timing modelsNorman P. Jouppi, Andrew B. Kahng, Naveen Muralimanohar, Vaishnav Srinivas. 294-301 [doi]
• AFReP: Application-guided Function-level Registerfile power-gating for embedded processorsHamed Tabkhi, Gunar Schirner. 302-308 [doi]
• Efficient multiple-bit retention register assignment for power gated design: Concept and algorithmsYu-Guang Chen, Yiyu Shi, Kuan-Yu Lai, Hui Geng, Shih-Chieh Chang. 309-316 [doi]
• A holistic analysis of circuit timing variations in 3D-ICs with thermal and TSV-induced stress considerationsSravan K. Marella, Sanjay V. Kumar, Sachin S. Sapatnekar. 317-324 [doi]
• Electromigration-aware routing for 3D ICs with stress-aware EM modelingJiwoo Pak, Sung Kyu Lim, David Z. Pan. 325-332 [doi]
• 3D transient thermal solver using non-conformal domain decomposition approachJianyong Xie, Madhavan Swaminathan. 333-340 [doi]
• Opening: Introduction to CAD contest at ICCAD 2012: CAD contestIris Hui-Ru Jiang, Zhuo Li, Yih-Lang Li. 341 [doi]
• ICCAD-2012 CAD contest in finding the minimal logic difference for functional ECO and benchmark suite: CAD contestWoeiTzy Jong, Hwei-Tseng Wang, Chengta Hsieh, Kei-Yong Khoo. 342-344 [doi]
• ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suiteNatarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Yaoguang Wei. 345-348 [doi]
• ICCAD-2012 CAD contest in fuzzy pattern matching for physical verification and benchmark suiteJ. Andres Torres. 349-350 [doi]
• System energy consumption is a multi-player gameMian Dong, Tian Lan, Lin Zhong. 351-352 [doi]
• Voltage-aware chip-level design for reliability-driven pin-constrained EWOD chipsSheng-Han Yeh, Jia-Wen Chang, Tsung-Wei Huang, Tsung-Yi Ho. 353-360 [doi]
• Compiling program control flows into biochemical reactionsDe-An Huang, Jie-Hong R. Jiang, Ruei-Yang Huang, Chi-Yun Cheng. 361-368 [doi]
• Dictionary-based error recovery in cyberphysical digital-microfluidic biochipsYan Luo, Krishnendu Chakrabarty, Tsung-Yi Ho. 369-376 [doi]
• Reactant minimization during sample preparation on digital microfluidic biochips using skewed mixing treesJuinn-Dar Huang, Chia-Hung Liu, Ting Wei Chiang. 377-383 [doi]
• Fast Transform-based preconditioners for large-scale power grid analysis on massively parallel architecturesKonstantis Daloukas, Nestoras E. Evmorfopoulos, George Drasidis, Michalis K. Tsiampas, Panagiota Tsompanopoulou, George I. Stamoulis. 384-391 [doi]
• Deterministic random walk preconditioning for power grid analysisJia Wang. 392-398 [doi]
• Efficient parallel power grid analysis via Additive Schwarz MethodTing Yu, Zigang Xiao, Martin D. F. Wong. 399-406 [doi]
• Circuit simulation via matrix exponential method for stiffness handling and parallel processingShih-Hung Weng, Quan Chen, Ngai Wong, Chung-Kuan Cheng. 407-414 [doi]
• An efficient control variates method for yield estimation of analog circuits based on a local modelPierre-Francois Desrumaux, Yoan Dupret, Jens Tingleff, Sean Minehane, Mark Redford, Laurent Latorre, Pascal Nouet. 415-421 [doi]
• A fast time-domain EM-TCAD coupled simulation framework via matrix exponentialQuan Chen, Wim Schoenmaker, Shih-Hung Weng, Chung-Kuan Cheng, Guan-Hua Chen, Lijun Jiang, Ngai Wong. 422-428 [doi]
• GPSCP: A general-purpose support-circuit preconditioning approach to large-scale SPICE-accurate nonlinear circuit simulationsXueqian Zhao, Zhuo Feng. 429-435 [doi]
• Verifying dynamic properties of nonlinear mixed-signal circuits via efficient SMT-based techniquesLeyi Yin, Yue Deng, Peng Li. 436-442 [doi]
• Toward codesign in high performance computing systemsRichard F. Barrett, Xiaobo Sharon Hu, Sudip S. Dosanjh, S. Parker, Michael A. Heroux, John Shalf. 443-449 [doi]
• Accurate on-chip router area modeling with Kriging methodologyFlorentine Dubois, Valerio Catalano, Marcello Coppola, Frédéric Pétrot. 450-457 [doi]
• Distributed memory interface synthesis for Network-on-Chips with 3D-stacked DRAMsYi-Jung Chen, Chia-Lin Yang, Jian-Jia Chen. 458-465 [doi]
• Efficient design space exploration for component-based system designYinghai Lu, Hai Zhou. 466-472 [doi]
• Multiple tunable constant multiplications: Algorithms and applicationsLevent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro. 473-479 [doi]
• The synthesis of complex arithmetic computation on stochastic bit streams using sequential logicPeng Li, David J. Lilja, Weikang Qian, Kia Bazargan, Marc D. Riedel. 480-487 [doi]
• Memory partitioning and scheduling co-optimization in behavioral synthesisPeng Li, Yuxin Wang, Peng Zhang, Guojie Luo, Tao Wang, Jason Cong. 488-495 [doi]
• Confronting and exploiting operating environment uncertainty in predictive analysis of signal integrityAndreas C. Cangellaris. 496 [doi]
• Multi-scale, multi-physics analysis for device, chip, package, and board levelWeng C. Chew. 497 [doi]
• Design strategies for high-dimensional electromagnetic systemsVikram Jandhyala, Arun V. Sathanur. 498 [doi]
• Co-simulations of electromagnetic and thermal effects in electronic circuits using non-conformal numerical methodsJin-Fa Lee, Yang Shao, Zhen Peng. 499 [doi]
• ISBA: An independent set-based algorithm for automated partial reconfiguration module generationRuining He, Yuchun Ma, Kang Zhao, Jinian Bian. 500-507 [doi]
• Fine-grained hardware/software methodology for process migration in MPSoCsTuo Li 0001, Jude Angelo Ambrose, Sri Parameswaran. 508-515 [doi]
• Active compensation technique for the thin-film transistor variations and OLED aging of mobile device displaysXiang Chen, Beiye Liu, Yiran Chen, Mengying Zhao, Chun Jason Xue, Xiaojun Guo. 516-522 [doi]
• Implementing high-performance, low-power embedded processors: Challenges and solutions: Designer trackKoen Lampaert. 523 [doi]
• Latency tolerance for Throughput Computing: Designer trackChien-Ping Lu, Brian Ko. 524-525 [doi]
• Multi-level cell STT-RAM: Is it realistic or just a dream?Yaojun Zhang, Lu Zhang, Wujie Wen, Guangyu Sun, Yiran Chen. 526-532 [doi]
• Ultra-low power NEMS FPGASijing Han, Vijay Sirigiri, Daniel G. Saab, Massood Tabib-Azar. 533-538 [doi]
• Ultra high density logic designs using transistor-level monolithic 3D integrationYoung-Joon Lee, Patrick Morrow, Sung Kyu Lim. 539-546 [doi]
• Challenges in post-silicon validation of high-speed I/O linksChenjie Gu. 547-550 [doi]
• Post-silicon performance modeling and tuning of analog/mixed-signal circuits via Bayesian Model FusionXin Li. 551-552 [doi]
• Validation signature testing: A methodology for post-silicon validation of analog/mixed-signal circuitsAbhijit Chatterjee, Sabyasachi Deyati, Barry John Muldrey, Shyam Kumar Devarakond, Aritra Banerjee. 553-556 [doi]
• Functional post-silicon diagnosis and debug for networks-on-chipRawan Abdel-Khalek, Valeria Bertacco. 557-563 [doi]
• TRACKER: A low overhead adaptive NoC router with load balancing selection strategyJohn Jose, K. V. Mahathi, J. Shiva Shankar, Madhu Mutyam. 564-568 [doi]
• Provably complete hardware Trojan detection using test point insertionSheng Wei, Kai Li, Farinaz Koushanfar, Miodrag Potkonjak. 569-576 [doi]
• Using standardized quantization for multi-party PPUF matching: Foundations and applicationsSaro Meguerdichian, Miodrag Potkonjak. 577-584 [doi]
• Simultaneous information flow security and circuit redundancy in Boolean gatesWei Hu, Jason Oberg, Dejun Mu, Ryan Kastner. 585-590 [doi]
• On logic synthesis for timing speculationYuxi Liu, Rong Ye, Feng Yuan, Rakesh Kumar, Qiang Xu. 591-596 [doi]
• Lazy man's logic synthesisWenlong Yang, Lingli Wang, Alan Mishchenko. 597-604 [doi]
• Minimizing area and power of sequential CMOS circuits using threshold decompositionNiranjan Kulkarni, Nishant Nukala, Sarma B. K. Vrudhula. 605-612 [doi]
• Performance-driven analog placement considering monotonic current pathsPo-Hsun Wu, Mark Po-Hung Lin, Yang-Ru Chen, Bing-Shiun Chou, Tung-Chieh Chen, Tsung-Yi Ho, Bin-Da Liu. 613-619 [doi]
• Configurable analog routing methodology via technology and design constraint unificationPo-Cheng Pan, Hung-Ming Chen, Yi-Kan Cheng, Jill Liu, Wei-Yi Hu. 620-626 [doi]
• Efficient parametric yield estimation of analog/mixed-signal circuits via Bayesian model fusionXin Li, Wangyang Zhang, Fa Wang, Shupeng Sun, Chenjie Gu. 627-634 [doi]
• Analytical-based approach for capacitor placement with gradient error compensation and device correlation enhancement in analog integrated circuitsCheng-Wu Lin, Chung-Lin Lee, Jai-Ming Lin, Soon-Jyh Chang. 635-642 [doi]
• 2012 TAU power grid simulation contest: Benchmark suite and resultsZhuo Li, Raju Balasubramanian, Frank Liu, Sani R. Nassif. 643-646 [doi]
• PGT_SOLVER: An efficient solver for power grid transient analysisTing Yu, Martin D. F. Wong. 647-652 [doi]
• PowerRush : Efficient transient simulation for power grid analysisJianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou. 653-659 [doi]
• Parallel forward and back substitution for efficient power grid simulationXuanxing Xiong, Jia Wang. 660-663 [doi]
• Design analysis of IC power deliveryPeng Li. 664-666 [doi]
• Power grid effects and their impact on-dieEli Chiprout. 667-669 [doi]
• Overview of vectorless/early power grid verificationFarid N. Najm. 670-677 [doi]
• Transistor technologies and pixel circuit design for efficient active-matrix organic light-emitting diode displaysXiaojun Guo, Guangyu Yao, Xiaoli Xu, Wenjiang Liu, Tao Liu. 678 [doi]
• Battery cell configuration for organic light emitting diode display in modern smartphones and tablet-PCsDonghwa Shin, Kitae Kim, Naehyuck Chang, Massoud Pedram. 679-686 [doi]
• Mobile devices user - The subscriber and also the publisher of real-time OLED display power management planYiran Chen, Xiang Chen, Mengying Zhao, Chun Jason Xue. 687-690 [doi]
• Clock mesh synthesis with gated local trees and activity driven register clusteringJianchao Lu, Xiaomi Mao, Baris Taskin. 691-697 [doi]
• Fast approximation for peak power driven voltage partitioning in almost linear timeJia Wang, Xiaodao Chen, Lin Liu, Shiyan Hu. 698-704 [doi]
• Multiobjective optimization of deadspace, a critical resource for 3D-IC integrationJohann Knechtel, Igor L. Markov, Jens Lienig, Matthias Thiele. 705-712 [doi]
• A fast maze-free routing congestion estimator with hybrid unilateral monotonic routingWen-Hao Liu, Yih-Lang Li, Cheng-Kok Koh. 713-719 [doi]
• A thermal and process variation aware MTJ switching model and its applications in soft error analysisPeiyuan Wang, Wei Zhang, Rajiv V. Joshi, Rouwaida Kanj, Yiran Chen. 720-727 [doi]
• Modeling and synthesis of quality-energy optimal approximate addersJin Miao, Ku He, Andreas Gerstlauer, Michael Orshansky. 728-735 [doi]
• Representative Critical Reliability Paths for low-cost and accurate on-chip aging evaluationShuo Wang, Jifeng Chen, Mohammad Tehranipoor. 736-741 [doi]
• High-Performance, Low-Power Resonant Clocking: Embedded tutorialMatthew R. Guthaus, Baris Taskin. 742-745 [doi]