Ashutosh Chakraborty - researchr alias

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Viewing Publication 1 - 24 from 24

2013

Cell transformations and physical design techniques for 3D monolithic integrated circuitsShashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Giovanni De Micheli. jetc, 9(3):19, 2013. [doi]

Skew Management of NBTI Impacted Gated Clock TreesAshutosh Chakraborty, David Z. Pan. tcad, 32(6):918-927, 2013. [doi]

2012

Reclaiming over-the-IP-block routing resources with buffering-aware rectilinear Steiner minimum tree constructionYilin Zhang, Ashutosh Chakraborty, Salim Chowdhury, David Z. Pan. iccad 2012: 137-143 [doi]

2011

CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuitsShashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Thomas Ernst, Olivier Faynot, David Z. Pan, Giovanni De Micheli. aspdac 2011: 336-343 [doi]

Controlling NBTI degradation during static burn-in testingAshutosh Chakraborty, David Z. Pan. aspdac 2011: 597-602 [doi]

2010

Stress-driven 3D-IC placement with TSV keep-out zone and regularity studyKrit Athikulwongse, Ashutosh Chakraborty, Jae-Seok Yang, David Z. Pan, Sung Kyu Lim. iccad 2010: 669-674 [doi]

Performance analysis of 3-D monolithic integrated circuitsShashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Vasilis F. Pavlidis, Giovanni De Micheli. 3dic 2010: 1-4 [doi]

Thermal-Aware Clock Tree Design to Increase Timing Reliability of Embedded SoCsAshutosh Chakraborty, Karthik Duraisami, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino. tcas, 57-I(10):2741-2752, 2010. [doi]

PASAP: power aware structured ASIC placementAshutosh Chakraborty, David Z. Pan. islped 2010: 395-400 [doi]

Skew management of NBTI impacted gated clock treesAshutosh Chakraborty, David Z. Pan. ispd 2010: 127-133 [doi]

Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility EnhancementAshutosh Chakraborty, Sean X. Shi, David Z. Pan. tcad, 29(10):1533-1545, 2010. [doi]

2009

Analysis and optimization of NBTI induced clock skew in gated clock treesAshutosh Chakraborty, Gokul Ganesan, Anand Rajaram, David Z. Pan. date 2009: 296-299 [doi]

RegPlace: a high quality open-source placement framework for structured ASICsAshutosh Chakraborty, Anurag Kumar, David Z. Pan. dac 2009: 442-447 [doi]

On stress aware active area sizing, gate sizing, and repeater insertionAshutosh Chakraborty, David Z. Pan. ispd 2009: 35-42 [doi]

2008

Implementation of a thermal management unit for canceling temperature-dependent clock skew variationsAshutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino. integration, 41(1):2-8, 2008. [doi]

Dynamic Thermal Clock Skew Compensation Using Tunable Delay BuffersAshutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino. tvlsi, 16(6):639-649, 2008. [doi]

Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon DevicesAshutosh Chakraborty, Sean X. Shi, David Z. Pan. date 2008: 849-855 [doi]

An integrated nonlinear placement framework with congestion and porosity aware buffer planningTung-Chieh Chen, Ashutosh Chakraborty, David Z. Pan. dac 2008: 702-707 [doi]

2006

Dynamic Management of Thermally-Induced Clock Skew: An Implementation PerspectiveAshutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino. patmos 2006: 214-224 [doi]

Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuitsAshutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino. iscas 2006: [doi]

Thermal resilient bounded-skew clock tree optimization methodologyAshutosh Chakraborty, Prassanna Sithambaram, Karthik Duraisami, Alberto Macii, Enrico Macii, Massimo Poncino. date 2006: 832-837 [doi]

Dynamic thermal clock skew compensation using tunable delay buffersAshutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino. islped 2006: 162-167 [doi]

2005

Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus EncodingAshutosh Chakraborty, Enrico Macii, Massimo Poncino. patmos 2005: 297-307 [doi]

2003

Low-Voltage, Double-Edge-Triggered Flip FlopPradeep Varma, Ashutosh Chakraborty. patmos 2003: 11-20 [doi]

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Publications by 'Ashutosh Chakraborty'

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2013

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2006

2005

2003

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