Table of Contents

• Fidelity metrics for estimation modelsHaris Javaid, Aleksandar Ignjatovic, Sri Parameswaran. 1-8 [doi]
• Fast performance evaluation of fixed-point systems with un-smooth operatorsKarthick Parashar, Daniel Menard, Romuald Rocher, Olivier Sentieys, David Novo, Francky Catthoor. 9-16 [doi]
• Variation-aware layout-driven scheduling for performance yield optimizationGregory Lucas, Deming Chen. 17-24 [doi]
• Analysis and optimization of SRAM robustness for double patterning lithographyVivek Joshi, Kanak Agarwal, David Blaauw, Dennis Sylvester. 25-31 [doi]
• WISDOM: Wire spreading enhanced decomposition of masks in Double Patterning LithographyKun Yuan, David Z. Pan. 32-38 [doi]
• Maximum-information storage system: Concept, implementation and applicationXin Li. 39-46 [doi]
• Multi-Wafer Virtual Probe: Minimum-cost variation characterization by exploring wafer-to-wafer correlationWangyang Zhang, Xin Li, Emrah Acar, Frank Liu, Rob A. Rutenbar. 47-54 [doi]
• On behavioral model equivalence checking for large analog/mixed signal systemsAmandeep Singh, Peng Li. 55-61 [doi]
• An algorithm for exploiting modeling error statistics to enable robust analog optimizationAshish Kumar Singh, Mario Lok, Kareem Ragab, Constantine Caramanis, Michael Orshansky. 62-69 [doi]
• A simple implementation of determinant decision diagramGuoyong Shi. 70-76 [doi]
• Aging analysis at gate and macro cell levelDominik Lorenz, Martin Barke, Ulf Schlichtmann. 77-84 [doi]
• Resilient microprocessor design for improving performance and energy efficiencyKeith A. Bowman, James W. Tschanz. 85-88 [doi]
• Process variation aware performance modeling and dynamic power management for multi-core systemsSiddharth Garg, Diana Marculescu, Sebastian Herbert. 89-92 [doi]
• Design-aware mask inspectionAbde Ali Kagalwalla, Puneet Gupta, Chris Progler, Steve McDonald. 93-99 [doi]
• SMATO: Simultaneous mask and target optimization for improving lithographic process windowShayak Banerjee, Kanak B. Agarwal, Michael Orshansky. 100-106 [doi]
• Template-mask design methodology for double patterning technologyChin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif. 107-111 [doi]
• Fast and lossless graph division method for layout decomposition using SPQR-treeWai-Shing Luk, Huiping Huang. 112-115 [doi]
• Design dependent process monitoring for back-end manufacturing cost reductionTuck Boon Chan, Aashish Pant, Lerong Cheng, Puneet Gupta. 116-122 [doi]
• SETS: Stochastic execution time scheduling for multicore systems by joint state space and Monte CarloNabeel Iqbal, Jörg Henkel. 123-130 [doi]
• Combining optimistic and pessimistic DVS scheduling: An adaptive scheme and analysisSimon Perathoner, Kai Lampka, Nikolay Stoimenov, Lothar Thiele, Jian-Jia Chen. 131-138 [doi]
• Unified theory of real-time task scheduling and dynamic voltage/frequency Scaling on MPSoCsHessam Kooti, Eli Bozorgzadeh. 139-142 [doi]
• In-place decomposition for robustness in FPGAJu-Yueh Lee, Zhe Feng 0002, Lei He. 143-148 [doi]
• MVP: Capture-power reduction with minimum-violations partitioning for delay testingZhen Chen, Krishnendu Chakrabarty, Dong Xiang. 149-154 [doi]
• Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designsSzu-Pang Mu, Yi-Ming Wang, Hao-Yu Yang, Mango Chia-Tso Chao, Shi-Hao Chen, Chih-Mou Tseng, Tsung-Ying Tsai. 155-161 [doi]
• A scalable quantitative measure of IR-drop effects for scan pattern generationMeng-Fan Wu, Kun-Han Tsai, Wu-Tung Cheng, Hsin-Cheih Pan, Jiun-Lang Huang, Augusli Kifli. 162-167 [doi]
• Trace signal selection to enhance timing and logic visibility in post-silicon validationHamid Shojaei, Azadeh Davoodi. 168-172 [doi]
• System-level impact of chip-level failure mechanisms and screensAnne Gattiker. 173-176 [doi]
• Cross-layer error resilience for robust systemsLarkhoon Leem, Hyungmin Cho, Hsiao-Heng Lee, Young Moon Kim, Yanjing Li, Subhasish Mitra. 177-180 [doi]
• Reliability, thermal, and power modeling and optimizationRobert P. Dick. 181-184 [doi]
• Symbolic system level reliability analysisMichael Glaß, Martin Lukasiewycz, Felix Reimann, Christian Haubelt, Jürgen Teich. 185-189 [doi]
• Hierarchical memory scheduling for multimedia MPSoCsYe-Jyun Lin, Chia-Lin Yang, Tay-Jyi Lin, Jiao-Wei Huang, Naehyuck Chang. 190-196 [doi]
• Credit Borrow and Repay: Sharing DRAM with minimum latency and bandwidth guaranteesZefu Dai, Mark Jarvin, Jianwen Zhu. 197-204 [doi]
• Scheduling of synchronous data flow models on scratchpad memory based embedded processorsWeijia Che, Karam S. Chatha. 205-212 [doi]
• The fast optimal voltage partitioning algorithm for peak power density minimizationJia Wang, Shiyan Hu. 213-217 [doi]
• Post-placement power optimization with multi-bit flip-flopsYao-Tsung Chang, Chih-Cheng Hsu, Mark Po-Hung Lin, Yu-Wen Tsai, Sheng-Fong Chen. 218-223 [doi]
• On power and fault-tolerance optimization in FPGA physical synthesisManu Jose, Yu Hu, Rupak Majumdar. 224-229 [doi]
• Yield enhancement for 3D-stacked memory by redundancy sharing across diesLi Jiang, Rong Ye, Qiang Xu. 230-234 [doi]
• Mathematical yield estimation for two-dimensional-redundancy memory arraysMango Chia-Tso Chao, Ching-Yu Chin, Chen-Wei Lin. 235-240 [doi]
• Analog test metrics estimates with PPM accuracyHaralampos-G. D. Stratigopoulos, Salvador Mir. 241-247 [doi]
• Design automation towards reliable analog integrated circuitsGeorges G. E. Gielen, Elie Maricau, Peter H. N. De Wit. 248-251 [doi]
• Digitalization of mixed-signal functionality in nanometer technologiesStephan Henzler. 252-255 [doi]
• Efficient trace-driven metaheuristics for optimization of networks-on-chip configurationsAndrew B. Kahng, Bill Lin, Kambiz Samadi, Rohit Sunkam Ramanujam. 256-263 [doi]
• A self-evolving design methodology for power efficient multi-core systemsJin Sun, Rui Zheng, Jyothi Velamala, Yu Cao, Roman L. Lysecky, Karthik Shankar, Janet Meiling Wang Roveda. 264-268 [doi]
• An energy and power-aware approach to high-level synthesis of asynchronous systemsJohn Hansen, Montek Singh. 269-276 [doi]
• Clustering-based simultaneous task and voltage scheduling for NoC systemsYifang Liu, Yu Yang, Jiang Hu. 277-283 [doi]
• Generalized nonlinear timing/phase macromodeling: Theory, numerical methods and applicationsChenjie Gu, Jaijeet S. Roychowdhury. 284-291 [doi]
• Phase equations for quasi-periodic oscillatorsAlper Demir, Chenjie Gu, Jaijeet S. Roychowdhury. 292-297 [doi]
• On-the-fly runtime adaptation for efficient execution of parallel multi-algorithm circuit simulationXiaoji Ye, Peng Li. 298-304 [doi]
• An auction based pre-processing technique to determine detour in global routingYue Xu, Chris Chu. 305-311 [doi]
• Simultaneous antenna avoidance and via optimization in layer assignment of multi-layer global routingTsung-Hsien Lee, Ting-Chi Wang. 312-318 [doi]
• GLADE: A modern global router considering layer directivesYen-Jung Chang, Tsung-Hsien Lee, Ting-Chi Wang. 319-323 [doi]
• Transaction level modeling in practice: Motivation and introductionGuido Stehr, Josef Eckmuuller. 324-331 [doi]
• Standards for System Level DesignLaurent Maillet-Contoz. 332-335 [doi]
• Design space exploration and performance evaluation at Electronic System Level for NoC-based MPSoCSören Sonntag, Francisco Gilabert Villamón. 336-339 [doi]
• ESL solutions for low power designSylvian Kaiser, Ilija Materic, Rabih Saade. 340-343 [doi]
• HW/SW co-design of parallel systemsEnno Wein. 344-348 [doi]
• Application specific processor design: Architectures, design methods and toolsAchim Nohl, Frank Schirrmeister, Drew Taussig. 349-352 [doi]
• Selective instruction set muting for energy-aware adaptive processorsMuhammad Shafique, Lars Bauer, Jörg Henkel. 353-360 [doi]
• Optimal algorithm for profile-based power gating: A compiler technique for reducing leakage on execution units in microprocessorsDanbee Park, Jungseob Lee, Nam Sung Kim, Taewhan Kim. 361-364 [doi]
• Memory access aware on-line voltage control for performance and energy optimizationXi Chen, Chi Xu, Robert P. Dick. 365-372 [doi]
• SPIRE: A retiming-based physical-synthesis transformation systemDavid A. Papa, Smita Krishnaswamy, Igor L. Markov. 373-380 [doi]
• Redundant-wires-aware ECO timing and mask cost optimizationShao-Yun Fang, Tzuo-Fan Chien, Yao-Wen Chang. 381-386 [doi]
• Through-silicon-via management during 3D physical design: When to add and how many?Mohit Pathak, Young-Joon Lee, Thomas Moon, Sung Kyu Lim. 387-394 [doi]
• Recent research development in PCB layoutTan Yan, Martin D. F. Wong. 398-403 [doi]
• Recent research development in flip-chip routingHsu-Chieh Lee, Yao-Wen Chang, Po-Wei Lee. 404-410 [doi]
• Modeling and design for beyond-the-die power integrityYiyu Shi, Lei He. 411-416 [doi]
• A synthesis flow for digital signal processing with biomolecular reactionsHua Jiang, Aleksandra P. Kharam, Marc D. Riedel, Keshab K. Parhi. 417-424 [doi]
• A network-flow based pin-count aware routing algorithm for broadcast electrode-addressing EWOD chipsTsung-Wei Huang, Shih-Yuan Yeh, Tsung-Yi Ho. 425-431 [doi]
• Variation tolerant sensing scheme of Spin-Transfer Torque Memory for yield improvementZhenyu Sun, Hai Li, Yiran Chen, XiaoBin Wang. 432-437 [doi]
• Novel binary linear programming for high performance clock mesh synthesisMinsik Cho, David Z. Pan, Ruchir Puri. 438-443 [doi]
• Low-power clock trees for CPUsDongJin Lee, Myung-Chul Kim, Igor L. Markov. 444-451 [doi]
• High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving treesXin-Wei Shih, Hsu-Chieh Lee, Kuan-Hsien Ho, Yao-Wen Chang. 452-457 [doi]
• Local clock skew minimization using blockage-aware mixed tree-mesh clock networkLinfu Xiao, Zigang Xiao, Zaichen Qian, Yan Jiang, Tao Huang, Haitong Tian, Evangeline F. Y. Young. 458-462 [doi]
• 3D-ICE: Fast compact transient thermal modeling for 3D ICs with inter-tier liquid coolingArvind Sridhar, Alessandro Vincenzi, Martino Ruggiero, Thomas Brunschwiler, David Atienza. 463-470 [doi]
• Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysisYibo Chen, Dimin Niu, Yuan Xie, Krishnendu Chakrabarty. 471-476 [doi]
• Evaluation of using inductive/capacitive-coupling vertical interconnects in 3D network-on-chipJin Ouyang, Jing Xie, Matthew Poremba, Yuan Xie. 477-482 [doi]
• Scalable segmentation-based malicious circuitry detection and diagnosisSheng Wei, Miodrag Potkonjak. 483-486 [doi]
• Application-Aware diagnosis of runtime hardware faultsAndrea Pellegrini, Valeria Bertacco. 487-492 [doi]
• Manufacturing and characteristics of low-voltage organic thin-film transistorsHagen Klauk, Ute Zschieschang. 493-495 [doi]
• Design and manufacturing of organic RFID circuits: Coping with intrinsic parameter variations in organic devices by circuit designJan Genoe, Kris Myny, Soeren Steudel, Paul Heremans. 496-499 [doi]
• Design of large area electronics with organic transistorsMakoto Takamiya, Koichi Ishida, Tsuyoshi Sekitani, Takao Someya, Takayasu Sakurai. 500-503 [doi]
• Design of analog circuits using organic field-effect transistorsBoris Murmann, Wei Xiong. 504-507 [doi]
• Active learning framework for post-silicon variation extraction and test cost reductionCheng Zhuo, Kanak Agarwal, David Blaauw, Dennis Sylvester. 508-515 [doi]
• Analysis of circuit dynamic behavior with timed ternary decision diagramLu Wan, Deming Chen. 516-523 [doi]
• Fast statistical timing analysis of latch-controlled circuits for arbitrary clock periodsBing Li, Ning Chen, Ulf Schlichtmann. 524-531 [doi]
• On timing-independent false path identificationFeng Yuan, Qiang Xu. 532-535 [doi]
• 3POr - Parallel projection based parameterized order reduction for multi-dimensional linear modelsJorge Fernandez Villena, Luis Miguel Silveira. 536-542 [doi]
• A hierarchical matrix inversion algorithm for vectorless power grid verificationXuanxing Xiong, Jia Wang. 543-550 [doi]
• Fast thermal analysis on GPU for 3D-ICs with integrated microchannel coolingZhuo Feng, Peng Li. 551-555 [doi]
• Native-conflict-aware wire perturbation for double patterning technologySzu-Yu Chen, Yao-Wen Chang. 556-561 [doi]
• A lower bound computation method for evaluation of statistical design techniquesVineeth Veetil, Dennis Sylvester, David Blaauw. 562-569 [doi]
• Timing yield optimization via discrete gate sizing using globally-informed delay PDFsShantanu Dutt, Huan Ren. 570-577 [doi]
• Digital microfluidic biochips: A vision for functional diversity and more than mooreTsung-Yi Ho, Jun Zeng, Krishnendu Chakrabarty. 578-585 [doi]
• Bi-decomposition of large Boolean functions using blocking edge graphsMihir R. Choudhury, Kartik Mohanram. 586-591 [doi]
• Peak current reduction by simultaneous state replication and re-encodingJunjun Gu, Gang Qu, Lin Yuan, Qiang Zhou. 592-595 [doi]
• Boolean matching of function vectors with strengthened learningChih-Fan Lai, Jie-Hong R. Jiang, Kuo-Hua Wang. 596-601 [doi]
• Reduction of interpolants for logic synthesisJohn D. Backes, Marc D. Riedel. 602-609 [doi]
• Obstacle-avoiding rectilinear Steiner minimum tree construction: An optimal approachTao Huang, Evangeline F. Y. Young. 610-613 [doi]
• On the escape routing of differential pairsTan Yan, Pei-Ci Wu, Qiang Ma 0002, Martin D. F. Wong. 614-620 [doi]
• New placement prediction and mitigation techniques for local routing congestionTaraneh Taghavi, Zhuo Li, Charles J. Alpert, Gi-Joon Nam, Andrew Huber, Shyam Ramji. 621-624 [doi]
• Misleading energy and performance claims in sub/near threshold digital systemsYu Pu, Xin Zhang, Jim Huang, Atsushi Muramatsu, Masahiro Nomura, Koji Hirairi, Hidehiro Takata, Taro Sakurabayashi, Shinji Miyano, Makoto Takamiya, Takayasu Sakurai. 625-631 [doi]
• Stretching the limit of microarchitectural level leakage control with Adaptive Light-Weight Vth HoppingHao Xu, Wen-Ben Jone, Ranga Vemuri. 632-636 [doi]
• Current shaping and multi-thread activation for fast and reliable power mode transition in multicore designsHao Xu, Ranga Vemuri, Wen-Ben Jone. 637-641 [doi]
• Fuzzy control for enforcing energy efficiency in high-performance 3D systemsMohamed M. Sabry, Ayse Kivilcim Coskun, David Atienza. 642-648 [doi]
• SimPL: An effective placement algorithmMyung-Chul Kim, DongJin Lee, Igor L. Markov. 649-656 [doi]
• Unified analytical global placement for large-scale mixed-size circuit designsMeng-Kai Hsu, Yao-Wen Chang. 657-662 [doi]
• Design-hierarchy aware mixed-size placement for routability optimizationYi-Lin Chuang, Gi-Joon Nam, Charles J. Alpert, Yao-Wen Chang, Jarrod A. Roy, Natarajan Viswanathan. 663-668 [doi]
• Stress-driven 3D-IC placement with TSV keep-out zone and regularity studyKrit Athikulwongse, Ashutosh Chakraborty, Jae-Seok Yang, David Z. Pan, Sung Kyu Lim. 669-674 [doi]
• Practical placement and routing techniques for analog circuit designsLinfu Xiao, Evangeline F. Y. Young, Xiaoyong He, K. P. Pun. 675-679 [doi]
• Characterizing the lifetime reliability of manycore processors with core-level redundancyLin Huang, Qiang Xu. 680-685 [doi]
• Electrical characterization of RF TSV for 3D multi-core and heterogeneous ICsLe Yu, Haigang Yang, Tom T. Jing, Min Xu, Robert Geer, Wei Wang. 686-693 [doi]
• Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D systemMinki Cho, Chang Liu, Dae-Hyun Kim, Sung Kyu Lim, Saibal Mukhopadhyay. 694-697 [doi]
• Fast Poisson solvers for thermal analysisHaifeng Qian, Sachin S. Sapatnekar. 698-702 [doi]
• Sequential importance sampling for low-probability and high-dimensional SRAM yield analysisKentaro Katayama, Shiho Hagiwara, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato. 703-708 [doi]
• Simulation of random telegraph Noise with 2-stage equivalent circuitYun Ye, Chi-Chao Wang, Yu Cao. 709-713 [doi]
• Work-function variation induced fluctuation in bias-temperature-instability characteristics of emerging metal-gate devices and implications for digital designSeid Hadi Rasouli, Kazuhiko Endo, Kaustav Banerjee. 714-720 [doi]
• Structured analog circuit design and MOS transistor decomposition for high accuracy applicationsBo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake. 721-728 [doi]
• A robust functional ECO engine by SAT proof minimization and interpolation techniquesBo-Han Wu, Chun-Ju Yang, Chung-Yang Huang, Jie-Hong Roland Jiang. 729-734 [doi]
• Efficient arithmetic sum-of-product (SOP) based Multiple Constant Multiplication (MCM) for FFTVinay Karkala, Joseph Wanstrath, Travis Lacour, Sunil P. Khatri. 735-738 [doi]
• Analysis of precision for scaling the intermediate variables in fixed-point arithmetic circuitsO. Sarbishei, Katarzyna Radecka. 739-745 [doi]
• Synthesis of an efficient controlling structure for post-silicon clock skew minimizationYu-Chien Kao, Hsuan-Ming Chou, Kun-Ting Tsai, Shih-Chieh Chang. 746-749 [doi]
• Engineering a scalable Boolean matching based on EDA SaaS 2.0Chun Zhang, Yu Hu, Lingli Wang, Lei He, Jiarong Tong. 750-755 [doi]
• Polynomial datapath optimization using constraint solving and formal modellingFinn Haedicke, Bijan Alizadeh, Görschwin Fey, Masahiro Fujita, Rolf Drechsler. 756-761 [doi]
• Online selection of effective functional test programs based on novelty detectionPo-Hsien Chang, Dragoljub Gagi Drmanac, Li-C. Wang. 762-769 [doi]
• Flexible interpolation with local proof transformationsRoberto Bruttomesso, Simone Rollini, Natasha Sharygina, Aliaksei Tsitovich. 770-777 [doi]
• Symbolic performance analysis of elastic systemsMarc Galceran Oms, Jordi Cortadella, Michael Kishinevsky. 778-785 [doi]
• Efficient state space exploration: Interleaving stateless and state-based model checkingMalay K. Ganai, Chao Wang, Weihong Li. 786-793 [doi]
• Formal deadlock checking on high-level SystemC designsChun-Nan Chou, Chang-Hong Hsu, Yueh-Tung Chao, Chung-Yang Huang. 794-799 [doi]
• PEDS: Passivity enforcement for descriptor systems via Hamiltonian-symplectic matrix pencil perturbationYuanzhe Wang, Zheng Zhang, Cheng-Kok Koh, Grantham K. H. Pang, Ngai Wong. 800-807 [doi]
• Power grid correction using sensitivity analysisMeric Aydonat, Farid N. Najm. 808-815 [doi]
• Early P/G grid voltage integrity verificationMehmet Avci, Farid N. Najm. 816-823 [doi]
• Characterization of the worst-case current waveform excitations in general RLC-model power grid analysisNestoras E. Evmorfopoulos, Maria-Aikaterini Rammou, George Stamoulis, John Moondanos. 824-830 [doi]