Timing yield optimization via discrete gate sizing using globally-informed delay PDFs - researchr publication

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Shantanu Dutt, Huan Ren. Timing yield optimization via discrete gate sizing using globally-informed delay PDFs. In 2010 International Conference on Computer-Aided Design (ICCAD 10), November 7-11, 2010, San Jose, CA, USA. pages 570-577, IEEE, 2010. [doi]

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