Masahiro Nomura - researchr alias

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Viewing Publication 1 - 46 from 46

2024

2023

2022

Benchmarking CMA-ES with margin on the bbob-mixint testbedRyoki Hamano, Shota Saito, Masahiro Nomura, Shinichi Shirakawa. gecco 2022: 1708-1716 [doi]

CMA-ES with margin: lower-bounding marginal probability for mixed-integer black-box optimizationRyoki Hamano, Shota Saito, Masahiro Nomura, Shinichi Shirakawa. gecco 2022: 639-647 [doi]

Towards a Principled Learning Rate Adaptation for Natural Evolution StrategiesMasahiro Nomura, Isao Ono. evoW 2022: 721-737 [doi]

Fast Moving Natural Evolution Strategy for High-Dimensional ProblemsMasahiro Nomura, Isao Ono. cec 2022: 1-8 [doi]

Multiobjective Tree-Structured Parzen EstimatorYoshihiko Ozaki, Yuki Tanigaki, Shuhei Watanabe, Masahiro Nomura, Masaki Onishi. jair, 73:1209-1250, 2022. [doi]

Towards Resolving Propensity Contradiction in Offline Recommender LearningYuta Saito, Masahiro Nomura. IJCAI 2022: 2211-2217 [doi]

2021

2020

Evaluating Initialization of Nelder-Mead Method for Hyperparameter Optimization in Deep LearningShintaro Takenaga, Shuhei Watanabe, Masahiro Nomura, Yoshihiko Ozaki, Masaki Onishi, Hitoshi Habe. icpr 2021: 3372-3379 [doi]

2019

Heat Transfer in Nanostructured Si and Heat Flux Control TechniqueMasahiro Nomura. 3dic 2019: 1-4 [doi]

H-EUC SecurityMasahiro Nomura, Katsuhiro Nakamura. ieicet, 102-A(1):125-147, 2019. [doi]

2014

Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic CircuitsHiroshi Fuketa, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai. jssc, 49(2):536-544, 2014. [doi]

2013

Variation-aware subthreshold logic circuit designHiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai. asicon 2013: 1-4 [doi]

Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuitsHiroshi Fuketa, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai. isscc 2013: 436-437 [doi]

DDmin-Aware Dual Supply Voltage TechniqueHiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai. tvlsi, 21(6):1175-1179, 2013. [doi]

Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic CircuitsHiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai. jssc, 48(8):1986-1994, 2013. [doi]

2012

Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuitsHiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai. cicc 2012: 1-4 [doi]

13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDOKoji Hirairi, Yasuyuki Okuma, Hiroshi Fuketa, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai. isscc 2012: 486-488 [doi]

A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay LinesYoshifumi Ikenaga, Masahiro Nomura, Shuji Suenaga, Hideo Sonohara, Yoshitaka Horikoshi, Toshiyuki Saito, Yukio Ohdaira, Yoichiro Nishio, Tomohiro Iwashita, Miyuki Satou, Koji Nishida, Koichi Nose, Koichiro Noguchi, Yoshihiro Hayashi, Masayuki Mizuno. jssc, 47(4):832-840, 2012. [doi]

Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low TemperatureRyo Takahashi, Hidehiro Takata, Tadashi Yasufuku, Hiroshi Fuketa, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai. tcas, 59-II(12):918-921, 2012. [doi]

DDmin limited ultra low voltage logic circuitsTadashi Yasufuku, Koji Hirairi, Yu Pu, Yun Fei Zheng, Ryo Takahashi, Masato Sasaki, Hiroshi Fuketa, Atsushi Muramatsu, Masahiro Nomura, Hirofumi Shinohara, Makoto Takamiya, Takayasu Sakurai. isqed 2012: 586-591 [doi]

2011

12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (V::DD::) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated V::DD:: between flip-flops and combinational logicsHiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai. islped 2010: 163-168 [doi]

DDmin) of CMOS logic gatesHiroshi Fuketa, Satoshi Iida, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai. dac 2011: 984-989 [doi]

Reduction of minimum operating voltage (V::DDmin::) of CMOS logic circuits with post-fabrication automatically selective charge injectionKentaro Honda, Katsuyuki Ikeuchi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai. islped 2010: 175-180 [doi]

12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domainsAtsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomura, Makoto Takamiya, Hirofumi Shinohara, Takayasu Sakurai. esscirc 2011: 191-194 [doi]

Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital CircuitsYu Pu, Xin Zhang, Katsuyuki Ikeuchi, Atsushi Muramatsu, Atsushi Kawasumi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai. tcas, 58-II(5):294-298, 2011. [doi]

Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMsKoichi Takeda, Toshio Saito, Shinobu Asayama, Yoshiharu Aimoto, Hiroyuki Kobatake, Shinya Ito, Toshifumi Takahashi, Masahiro Nomura, Kiyoshi Takeuchi, Yoshihiro Hayashi. jssc, 46(4):806-814, 2011. [doi]

Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOSTadashi Yasufuku, Satoshi Iida, Hiroshi Fuketa, Koji Hirairi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai. islped 2010: 21-26 [doi]

2010

Misleading energy and performance claims in sub/near threshold digital systemsYu Pu, Xin Zhang, Jim Huang, Atsushi Muramatsu, Masahiro Nomura, Koji Hirairi, Hidehiro Takata, Taro Sakurabayashi, Shinji Miyano, Makoto Takamiya, Takayasu Sakurai. iccad 2010: 625-631 [doi]

2008

A Circuit for Determining the Optimal Supply Voltage to Minimize Energy Consumption in LSI Circuit OperationsYoshifumi Ikenaga, Masahiro Nomura, Yoetsu Nakazawa, Yasuhiko Hagihara. jssc, 43(4):911-918, 2008. [doi]

2006

1999

A 2000-MOPS embedded RISC processor with a Rambus DRAM controllerKazumasa Suzuki, Masayuki Daito, Tomoo Inoue, Kouhei Nadehara, Masahiro Nomura, Masayuki Mizuno, Tomofumi Iima, Shoichiro Sato, Terumi Fukuda, Tomohisa Arai, Ichiro Kuroda, Masakazu Yamashina. jssc, 34(7):1010-1021, 1999. [doi]

1994

1990

Modular Design of Multiple-Valued Arithmetic VLSI System Using Signed-Digit Number SystemMichitaka Kameyama, Masahiro Nomura, Tatsuo Higuchi. ismvl 1990: 355-362

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