Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature

Ryo Takahashi, Hidehiro Takata, Tadashi Yasufuku, Hiroshi Fuketa, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai. Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature. IEEE Trans. on Circuits and Systems, 59-II(12):918-921, 2012. [doi]

Abstract

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