Shinya Ito - researchr alias

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Viewing Publication 1 - 15 from 15

2025

First Live Demonstration of Remote Controllable SFP28 APN-Transceiver for Mobile Fronthaul Use CasesYuya Saito, Naoki Umezawa, Yasuhiro Takizawa, Manabu Kotani, Shinya Ito, Shinichi Koyama, Yasuhiro Tanaka, Daisuke Umeda. ofc 2025: 1-3 [doi]

2021

Nonlinear visuoauditory integration in the mouse superior colliculusShinya Ito, Yufei Si, Alan M. Litke, David A. Feldheim. ploscb, 17(11), 2021. [doi]

2017

Impact of generator failures on photovoltaic energy curtailment in power systems with large-scale integration of photovoltaic generationTaisuke Masuta, Shinya Ito, Daiki Kobauashi, Hideaki Ohtake. iciis 2017: 1-6 [doi]

2016

High-Degree Neurons Feed Cortical ComputationsNicholas Timme, Shinya Ito, Maxym Myroshnychenko, Sunny Nigam, Masanori Shimono, Fang-Chin Yeh, Pawel Hottowy, Alan M. Litke, John M. Beggs. ploscb, 12(5), 2016. [doi]

2011

Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMsKoichi Takeda, Toshio Saito, Shinobu Asayama, Yoshiharu Aimoto, Hiroyuki Kobatake, Shinya Ito, Toshifumi Takahashi, Masahiro Nomura, Kiyoshi Takeuchi, Yoshihiro Hayashi. jssc, 46(4):806-814, 2011. [doi]

2007

2006

A method of digital watermarking by using the frequency masking effectShinya Ito, Hiroshi Tsubokawa. scjapan, 37(11):79-87, 2006. [doi]

2004

The Microarchitecture of the CUE-v2 Processor: Enabling the Simultaneous Processing of Dataflow and Control-Flow ThreadsShinya Ito, Shouhei Nomoto, Hiroshi Tomiyasu, Hiroaki Nishikawa. pdpta 2004: 525-531

2002

A Self-evolutionary Emulation Scheme for A Networking Oriented Data-driven Processor Architecture: CUEShinya Ito, Ryosuke Kurebayashi, Hiroaki Nishikawa. pdpta 2002: 1082-1088

Effect of mechanical stress induced by etch-stop nitride: impact on deep-submicron transistor performanceShinya Ito, Hiroaki Namba, Tsuyoshi Hirata, Koichi Ando, Shin Koyama, Nobuyuki Ikezawa, Tatsuya Suzuki, Takehiro Saitoh, Tadahiko Horiuchi. mr, 42(2):201-209, 2002. [doi]

2001

An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shieldKenji Noda, Koichi Takeda 0001, Koujirou Matsui, Shinya Ito, Sadaaki Masuoka, Hideaki Kawamoto, Nobuyuki Ikezawa, Yoshiharu Aimoto, Noritsugu Nakamura, Takahiro Iwasaki, Hideo Toyoshima, Tadahiko Horiuchi. jssc, 36(3):510-515, 2001. [doi]

2000

An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shieldKenji Noda, Koujirou Matsui, Shinya Ito, Sadaaki Masuoka, Hiroyuki Kawamoto, Nobuyuki Ikezawa, Koichi Takeda 0001, Yoshiharu Aimoto, Naoto Nakamura, Hideo Toyoshima, Takahiro Iwasaki, Tadahiko Horiuchi. cicc 2000: 283-286 [doi]

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