Noritsugu Nakamura - researchr alias

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Viewing Publication 1 - 7 from 7

2018

New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI ApplicationsTaro Fujii, Takao Toi, Teruhito Tanaka, Katsumi Togawa, Toshiro Kitaoka, Kengo Nishino, Noritsugu Nakamura, Hiroki Nakahara, Masato Motomura. vlsic 2018: 41-42 [doi]

2016

Constructing a Human-like agent for the Werewolf Game using a psychological model based multiple perspectivesNoritsugu Nakamura, Michimasa Inaba, Kenichi Takahashi, Fujio Toriumi, Hirotaka Osawa, Daisuke Katagami, Kousuke Shinoda. ssci 2016: 1-8 [doi]

2013

Optimizing time and space multiplexed computation in a dynamically reconfigurable processorTakao Toi, Noritsugu Nakamura, Taro Fujii, Toshiro Kitaoka, Katsumi Togawa, Koichiro Furuta, Toru Awashima. fpt 2013: 106-111 [doi]

2010

High-level Synthesis Challenges for Mapping a Complete Program on a Dynamically Reconfigurable ProcessorTakao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi. ipsj, 3:91-104, 2010. [doi]

2006

High-level synthesis challenges and solutions for a dynamically reconfigurable processorTakao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi, Li Jing. iccad 2006: 702-708 [doi]

2001

An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shieldKenji Noda, Koichi Takeda 0001, Koujirou Matsui, Shinya Ito, Sadaaki Masuoka, Hideaki Kawamoto, Nobuyuki Ikezawa, Yoshiharu Aimoto, Noritsugu Nakamura, Takahiro Iwasaki, Hideo Toyoshima, Tadahiko Horiuchi. jssc, 36(3):510-515, 2001. [doi]

2000

A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macroKoichi Takeda 0001, Yoshiharu Aimoto, Noritsugu Nakamura, Hideo Toyoshima, Takahiro Iwasaki, Kenji Noda, Koujirou Matsui, Shinya Itoh, Sadaaki Masuoka, Tadahiko Horiuchi, Atsushi Nakagawa, Kenju Shimogawa, Hiroyuki Takahashi. jssc, 35(11):1631-1640, 2000. [doi]

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