Table of Contents

• Stable and compact inductance modeling of 3-D interconnect structuresHong Li, Venkataramanan Balakrishnan, Cheng-Kok Koh. 1-6 [doi]
• A fast block structure preserving model order reduction for inverse inductance circuitsHao Yu, Yiyu Shi, Lei He, David Smart. 7-12 [doi]
• Fullwave volumetric Maxwell solver using conduction modesSalvador Ortiz, Roberto Suaya. 13-18 [doi]
• Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimizationMurari Mani, Ashish Kumar Singh, Michael Orshansky. 19-26 [doi]
• Optimal useful clock skew scheduling in the presence of variations using robust ILP formulationsVaibhav Nawale, Thomas W. Chen. 27-32 [doi]
• State re-encoding for peak current minimizationShih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh. 33-38 [doi]
• A statistical framework for post-silicon tuning through body bias clusteringSarvesh H. Kulkarni, Dennis Sylvester, David Blaauw. 39-46 [doi]
• A gate delay model focusing on current fluctuation over wide-range of process and environmental variabilityKenichi Shinkai, Masanori Hashimoto, Atsushi Kurokawa, Takao Onoye. 47-53 [doi]
• Practical variation-aware interconnect delay and slew analysis for statistical timing verificationXiaoji Ye, Peng Li, Frank Liu. 54-59 [doi]
• Analysis and modeling of CD variation for statistical static timingBrian Cline, Kaviraj Chopra, David Blaauw, Yu Cao. 60-66 [doi]
• From single core to multi-core: preparing for a new exponentialJeff Parkhurst, John A. Darringer, Bill Grundmann. 67-72 [doi]
• UML for ESL design: basic principles, tools, and applicationsWolfgang Mueller, Alberto Rosti, Sara Bocchio, Elvinia Riccobene, Patrizia Scandurra, Wim Dehaene, Yves Vanderperren. 73-80 [doi]
• On bounding the delay of a critical pathLeonard Lee, Li-C. Wang. 81-88 [doi]
• A delay fault model for at-speed fault simulation and test generationIrith Pomeranz, Sudhakar M. Reddy. 89-95 [doi]
• Efficient Boolean characteristic function for fast timed ATPGYu-Min Kuo, Yue-Lung Chang, Shih-Chieh Chang. 96-99 [doi]
• Exploring linear structures of critical path delay faults to reduce test effortsShun-Yen Lu, Pei-Ying Hsieh, Jing-Jia Liou. 100-106 [doi]
• Fast decap allocation based on algebraic multigridCheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen. 107-111 [doi]
• Precise identification of the worst-case voltage drop conditions in power grid verificationNestoras E. Evmorfopoulos, Dimitris P. Karampatzakis, Georgios I. Stamoulis. 112-118 [doi]
• Importance of volume discretization of single and coupled interconnectsAhmed Shebaita, Dusan Petranovic, Yehea I. Ismail. 119-126 [doi]
• Handling inductance in early power grid verificationNahi H. Abdul Ghani, Farid N. Najm. 127-134 [doi]
• Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAsGordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown. 135-142 [doi]
• Factor cutsSatrajit Chatterjee, Alan Mishchenko, Robert K. Brayton. 143-150 [doi]
• An efficient technique for synthesis and optimization of polynomials in GF(2:::::::m:::::::)Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew. 151-157 [doi]
• Cost-aware synthesis of asynchronous circuits based on partial acknowledgementYu Zhou, Danil Sokolov, Alexandre Yakovlev. 158-163 [doi]
• A revisit to floorplan optimization by Lagrangian relaxationChuan Lin, Hai Zhou, Chris C. N. Chu. 164-171 [doi]
• Fast wire length estimation by net bundling for block placementTan Yan, Hiroshi Murata. 172-178 [doi]
• Fast and robust quadratic placement combined with an exact linear net modelPeter Spindler, Frank M. Johannes. 179-186 [doi]
• A high-quality mixed-size analytical placer considering preplaced blocks and density constraintsTung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang. 187-192 [doi]
• Testing delay faults in asynchronous handshake circuitsFeng Shi, Yiorgos Makris. 193-197 [doi]
• A novel framework for faster-than-at-speed delay test considering IR-drop effectsNisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram. 198-203 [doi]
• Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniquesMihir R. Choudhury, Quming Zhou, Kartik Mohanram. 204-209 [doi]
• Enhanced error vector magnitude (EVM) measurements for testing WLAN transceiversErkan Acar, Sule Ozev, Kevin B. Redmond. 210-216 [doi]
• A linear-time approach for static timing analysis covering all process cornersSari Onaissi, Farid N. Najm. 217-224 [doi]
• A framework for statistical timing analysis using non-linear delay and slew modelsSarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula. 225-230 [doi]
• An accurate sparse matrix based framework for statistical static timing analysisAnand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan. 231-236 [doi]
• A new statistical max operation for propagating skewness in statistical timing analysisKaviraj Chopra, Bo Zhai, David Blaauw, Dennis Sylvester. 237-243 [doi]
• Cache miss clustering for banked memory systemsOzcan Ozturk, G. Chen, Mahmut T. Kandemir, Mustafa Karaköy. 244-250 [doi]
• A bitmask-based code compression technique for embedded systemsSeok-Won Seong, Prabhat Mishra. 251-254 [doi]
• Allocation cost minimization for periodic hard real-time tasks in energy-constrained DVS systemsJian-Jia Chen, Tei-Wei Kuo. 255-260 [doi]
• Application-specific customization of parameterized FPGA soft-core processorsDavid Sheldon, Rakesh Kumar, Roman L. Lysecky, Frank Vahid, Dean M. Tullsen. 261-268 [doi]
• TP-PPV: piecewise nonlinear, time-shifted oscillator macromodel extraction for fast, accurate PLL simulationXiaolue Lai, Jaijeet S. Roychowdhury. 269-274 [doi]
• Verification of analog/mixed-signal circuits using labeled hybrid petri netsScott Little, Nicholas Seegmiller, David Walter, Chris J. Myers, Tomohiro Yoneda. 275-282 [doi]
• PPV-HB: harmonic balance for oscillator/PLL phase macromodelsTing Mei, Jaijeet S. Roychowdhury. 283-288 [doi]
• Loop pipelining for high-throughput stream computation using self-timed ringsGennette Gill, John Hansen, Montek Singh. 289-296 [doi]
• Thermal-induced leakage power optimization by redundant resource allocationMin Ni, Seda Ogrenci Memik. 297-302 [doi]
• Guaranteeing performance yield in high-level synthesisWei-Lun Hung, Xiaoxia Wu, Yuan Xie. 303-309 [doi]
• Information theoretic approach to address delay and reliability in long on-chip interconnectsRohit Singhal, Gwan S. Choi, Rabi N. Mahapatra. 310-314 [doi]
• Analytical modeling of SRAM dynamic stabilityBin Zhang, Ari Arapostathis, Sani R. Nassif, Michael Orshansky. 315-322 [doi]
• A high-level compact pattern-dependent delay model for high-speed point-to-point interconnectsTudor Murgan, Massoud Momeni, Alberto García Ortiz, Manfred Glesner. 323-328 [doi]
• Design and CAD challenges in 45nm CMOS and beyondDavid J. Frank, Ruchir Puri, Dorel Toma. 329-333 [doi]
• Robust system level design with analog platformsFernando De Bernardinis, Pierluigi Nuzzo, Alberto L. Sangiovanni-Vincentelli. 334-341 [doi]
• Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layoutsNuttorn Jangkrajarng, Lihong Zhang, Sambuddha Bhattacharya, Nathan Kohagen, C.-J. Richard Shi. 342-348 [doi]
• Analog placement with symmetry and other placement constraintsYiu-Cheong Tam, Evangeline F. Y. Young, Chris C. N. Chu. 349-354 [doi]
• Designing application-specific networks on chips with floorplan informationSrinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo. 355-362 [doi]
• Fast and accurate transaction level models using result oriented modelingGunar Schirner, Rainer Dömer. 363-368 [doi]
• Optimal memoryless encoding for low power off-chip data busesYeow Meng Chee, Charles J. Colbourn, Alan C. H. Ling. 369-374 [doi]
• A network-flow approach to timing-driven incremental placement for ASICsShantanu Dutt, Huan Ren, Fenghua Yuan, Vishal Suthar. 375-382 [doi]
• Timing-driven placement for heterogeneous field programmable gate arrayBo Hu. 383-388 [doi]
• Voltage island aware floorplanning for power and timing optimizationWan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang. 389-394 [doi]
• Decoupling capacitor planning and sizing for noise and leakage reductionEric Wong, Jacob R. Minz, Sung Kyu Lim. 395-400 [doi]
• A timing dependent power estimation framework considering couplingDebjit Sinha, DiaaEldin Khalil, Yehea I. Ismail, Hai Zhou. 401-407 [doi]
• Algorithms for MIS vector generation and pruningKenneth S. Stevens, Florentin Dartu. 408-414 [doi]
• Timing model reduction for hierarchical timing analysisShuo Zhou, Yi Zhu, Yuanfang Hu, Ronald L. Graham, Mike Hutton, Chung-Kuan Cheng. 415-422 [doi]
• A unified non-rectangular device and circuit simulation model for timing and powerSean X. Shi, Peng Yu, David Z. Pan. 423-428 [doi]
• Microarchitecture parameter selection to optimize system performance under process variationXiaoyao Liang, David Brooks. 429-436 [doi]
• Thermal sensor allocation and placement for reconfigurable systemsRajarshi Mukherjee, Somsubhra Mondal, Seda Ogrenci Memik. 437-442 [doi]
• Thermal characterization and optimization in platform FPGAsPriya Sundararajan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan. 443-447 [doi]
• Performance analysis of concurrent systems with early evaluationJorge Júlvez, Jordi Cortadella, Michael Kishinevsky. 448-455 [doi]
• Near-term industrial perspective of analog CADChristopher Labrecque. 456-457 [doi]
• Design automation for analog: the next generation of tool challengesRob A. Rutenbar. 458-460 [doi]
• Automation in mixed-signal design: challenges and solutions in the wake of the nano eraTrent McConaghy, Georges G. E. Gielen. 461-463 [doi]
• FastRoute: a step to integrate global routing into placementMin Pan, Chris C. N. Chu. 464-471 [doi]
• Trunk decomposition based global routing optimizationDevang Jariwala, John Lillis. 472-479 [doi]
• Optimizing yield in global routingDirk Müller. 480-486 [doi]
• Wire density driven global routing for CMP variation and timingMinsik Cho, David Z. Pan, Hua Xiang, Ruchir Puri. 487-492 [doi]
• An analytical model for negative bias temperature instabilitySanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar. 493-496 [doi]
• Soft error derating computation in sequential circuitsHossein Asadi, Mehdi Baradaran Tahoori. 497-501 [doi]
• Soft error reduction in combinational logic using gate resizing and flipflop selectionRajeev R. Rao, David Blaauw, Dennis Sylvester. 502-509 [doi]
• Current path analysis for electrostatic discharge protectionHung-Yi Liu, Chung-Wei Lin, Szu-Jui Chou, Wei-Ting Tu, Chih-Hung Liu, Yao-Wen Chang, Sy-Yen Kuo. 510-515 [doi]
• System-wide energy minimization for real-time tasks: lower bound and approximationXiliang Zhong, Cheng-Zhong Xu. 516-521 [doi]
• Online task-scheduling for fault-tolerant low-energy real-time systemsTongquan Wei, Piyush Mishra, Kaijie Wu, Han Liang. 522-527 [doi]
• Energy management for real-time embedded systems with reliability requirementsDakai Zhu, Hakan Aydin. 528-534 [doi]
• Exploiting soft redundancy for error-resilient on-chip memory designShuo Wang, Lei Wang. 535-540 [doi]
• System-level process-driven variability analysis for single and multiple voltage-frequency island systemsDiana Marculescu, Siddharth Garg. 541-546 [doi]
• Physical aware frequency selection for dynamic thermal management in multi-core systemsRajarshi Mukherjee, Seda Ogrenci Memik. 547-552 [doi]
• A new RLC buffer insertion algorithmZhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo Li, Weiping Shi. 553-557 [doi]
• Clock buffer polarity assignment for power noise reductionRupak Samanta, Ganesh Venkataraman, Jiang Hu. 558-562 [doi]
• Combinatorial algorithms for fast clock mesh optimizationGanesh Venkataraman, Zhuo Feng, Jiang Hu, Peng Li. 563-567 [doi]
• An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot managementSheng-Chih Lin, Kaustav Banerjee. 568-574 [doi]
• Adaptive multi-domain thermal modeling and analysis for integrated circuit synthesis and designYonghong Yang, Changyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert P. Dick. 575-582 [doi]
• Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuitsJung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy. 583-586 [doi]
• Runtime distribution-aware dynamic voltage scalingSungpack Hong, Sungjoo Yoo, HoonSang Jin, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo. 587-594 [doi]
• Formal model of data reuse analysis for hierarchical memory organizationsIlie I. Luican, Hongwei Zhu, Florin Balasa. 595-600 [doi]
• An adaptive two-level management for the flash translation layer in embedded systemsChin-Hsien Wu, Tei-Wei Kuo. 601-606 [doi]
• Design and integration methods for a multi-threaded dual core 65nm Xeon® processorRaj Varada, Mysore Sriram, Kris Chou, James Guzzo. 607-610 [doi]
• Counterflow pipelining: architectural support for preemption in asynchronous systems using anti-tokensManoj Ampalam, Montek Singh. 611-618 [doi]
• A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolationSwaroop Ghosh, Swarup Bhunia, Kaushik Roy. 619-624 [doi]
• Efficient process-hotspot detection using range pattern matchingHailong Yao, Subarna Sinha, Charles Chiang, Xianlong Hong, Yici Cai. 625-632 [doi]
• Post-routing redundant via insertion and line end extension with via density considerationKuang-Yao Lee, Ting-Chi Wang, Kai-Yuan Chao. 633-640 [doi]
• Post-placement voltage island generationRoyce L. S. Ching, Evangeline F. Y. Young, Kevin C. K. Leung, Chris C. N. Chu. 641-646 [doi]
• Prospects for emerging nanoelectronics in mainstream information processing systemsJeffrey Bokor. 647-648 [doi]
• Carbon nanotubes for potential electronic and optoelectronic applicationsJia Chen. 649-650 [doi]
• Carbon nanotube transistor circuits: models and tools for design and performance optimizationH.-S. Philip Wong, Jie Deng, Arash Hazeghi, Tejas Krishnamohan, Gordon C. Wan. 651-654 [doi]
• Technology migration techniques for simplified layouts with restrictive design rulesXiaoping Tang, Xin Yuan. 655-660 [doi]
• Fill for shallow trench isolation CMPAndrew B. Kahng, Puneet Sharma, Alexander Zelikovsky. 661-668 [doi]
• An optimal simultaneous diode/jumper insertion algorithm for antenna fixingZhe-Wei Jiang, Yao-Wen Chang. 669-674 [doi]
• Performances improvement of FPGA using novel multilevel hierarchical interconnection structureHayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez. 675-679 [doi]
• Un/DoPack: re-clustering of large system-on-chip designs with interconnect variation for low-cost FPGAsMarvin Tom, David Leong, Guy G. Lemieux. 680-687 [doi]
• Studying a GALS FPGA architecture using a parameterized automatic design flowXin Jia, Ranga Vemuri. 688-693 [doi]
• Conjoining soft-core FPGA processorsDavid Sheldon, Rakesh Kumar, Frank Vahid, Dean M. Tullsen, Roman L. Lysecky. 694-701 [doi]
• High-level synthesis challenges and solutions for a dynamically reconfigurable processorTakao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi, Li Jing. 702-708 [doi]
• Platform-based resource binding using a distributed register-file microarchitectureJason Cong, Yiping Fan, Wei Jiang. 709-715 [doi]
• A code refinement methodology for performance-improved synthesis from CGreg Stitt, Frank Vahid, Walid A. Najjar. 716-723 [doi]
• Leveraging protocol knowledge in slack matchingGirish Venkataramani, Seth Copen Goldstein. 724-729 [doi]
• Application-independent defect-tolerant crossbar nano-architecturesMehdi Baradaran Tahoori. 730-734 [doi]
• Nanowire addressing with randomized-contact decodersEric Rachlin, John E. Savage. 735-742 [doi]
• On the use of Bloom filters for defect maps in nanocomputingGang Wang, Wenrui Gong, Ryan Kastner. 743-746 [doi]
• Dynamic power management using machine learningGaurav Dhiman, Tajana Simunic Rosing. 747-754 [doi]
• Dynamic voltage and frequency management based on variable update intervals for frequency settingMehrdad Najibi, M. Salehi, Ali Afzali-Kusha, Massoud Pedram, Seid Mehdi Fakhraie, Hossein Pedram. 755-760 [doi]
• Temperature-aware leakage minimization technique for real-time systemsLin Yuan, Sean Leventhal, Gang Qu. 761-764 [doi]
• Energy budgeting for battery-powered sensors with a known task scheduleDaler N. Rakhmatov. 765-771 [doi]
• Stepping forward with interpolants in unbounded model checkingGianpiero Cabodi, Marco Murciano, Sergio Nocco, Stefano Quer. 772-778 [doi]
• Decomposing image computation for symbolic reachability analysis using control flow informationDavid Ward, Fabio Somenzi. 779-785 [doi]
• Automatic memory reductions for RTL model verificationPanagiotis Manolios, Sudarshan K. Srinivasan, Daron Vroon. 786-793 [doi]
• Accelerating high-level bounded model checkingMalay K. Ganai, Aarti Gupta. 794-801 [doi]
• Simultaneous power and thermal integrity driven via stapling in 3D ICsHao Yu, Joanna Ho, Lei He. 802-808 [doi]
• Yield prediction for 3D capacitive interconnectionsAlberto Fazzi, L. Magagni, Mario de Dominicis, Paolo Zoffoli, Roberto Canegallo, Pier Luigi Rolandi, Alberto L. Sangiovanni-Vincentelli, Roberto Guerrieri. 809-814 [doi]
• Layer minimization of escape routing in area array packagingRenshen Wang, Rui Shi, Chung-Kuan Cheng. 815-819 [doi]
• Network coding for routability improvement in VLSINikhil Jayakumar, Sunil P. Khatri, Kanupriya Gulati, Alexander Sprintson. 820-823 [doi]
• From micro to nano: MEMS as an interface to the nano worldBernhard E. Boser. 824-825 [doi]
• CMOS-MEMS integration: why, how and what?Ann Witvrouw. 826-827 [doi]
• Information processing in nanoscale arrays: DNA assembly, molecular devices, nano-array architecturesRichard A. Kiehl. 828-829 [doi]
• Molecular organic electronic circuitsVladimir Bulovi, Kevin Ryu, Charles Sodini, Ioannis Kymissis, Annie Wang, Ivan Nausieda, Akintunde Ibitayo Akinwande. 830-831 [doi]
• Organic electronic device modeling at the nanoscaleConor F. Madigan, Vladimir Bulovic. 832-833 [doi]
• Variability and yield improvement: rules, models, and characterizationKenneth L. Shepard, Daniel N. Maynard. 834-835 [doi]
• Improvements to combinational equivalence checkingAlan Mishchenko, Satrajit Chatterjee, Robert K. Brayton, Niklas Eén. 836-843 [doi]
• SMT(::::CLU::::): a step toward scalability in system verificationHossein M. Sheini, Karem A. Sakallah. 844-851 [doi]
• Solving the minimum-cost satisfiability problem using SAT based branch-and-bound searchZhaohui Fu, Sharad Malik. 852-859 [doi]
• Verification through the principle of least astonishmentBeth Isaksen, Valeria Bertacco. 860-867 [doi]
• Performance-oriented statistical parameter reduction of parameterized systems via reduced rank regressionZhuo Feng, Peng Li. 868-875 [doi]
• Faster, parametric trajectory-based macromodels via localized linear reductionsSaurabh K. Tiwary, Rob A. Rutenbar. 876-883 [doi]
• Robust estimation of parametric yield under limited descriptions of uncertaintyWei-Shen Wang, Michael Orshansky. 884-890 [doi]
• From molecular interactions to gates: a systematic approachJosep Carmona, Jordi Cortadella, Yousuke Takada, Ferdinand Peper. 891-898 [doi]
• A spectrally accurate integral equation solver for molecular surface electrostaticsShih-Hsien Kuo, Jacob White. 899-906 [doi]
• Using CAD to shape experiments in molecular QCAMichael T. Niemier, Michael Crocker, Xiaobo Sharon Hu, Marya Lieberman. 907-914 [doi]