Debjit Sinha - researchr alias

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Viewing Publication 1 - 33 from 33

2021

Technology Lookup Table based Default Timing Assertions for Hierarchical Timing ClosureRavi Ledalla, Debjit Sinha, Adil Bhanji, Chaobo Li, Gregory Schaeffer, Hemlata Gupta, Jennifer Basile. date 2021: 1558-1563 [doi]

2020

Statistical Timing Analysis considering Multiple-Input SwitchingDebjit Sinha, Vasant Rao, Chaitanya Peddawad, Michael H. Wood, Jeffrey G. Hemmett, Suriya Skariah, Patrick Williams. dac 2020: 1-6 [doi]

2016

A distributed timing analysis framework for large designsTsung-Wei Huang, Martin D. F. Wong, Debjit Sinha, Kerim Kalafala, Natesan Venkateswaran. dac 2016: 116 [doi]

Statistical path tracing in timing graphsVasant Rao, Debjit Sinha, Nitin Srimal, Prabhat K. Maurya. dac 2016: 114 [doi]

Sharing and Re-use of Statistical Timing Macro-Models across Multiple Voltage DomainsDebjit Sinha, Vladimir Zolotov, Eric Fluhr, Michael Wood, Jeffrey Ritzinger, Natesan Venkateswaran, Stephen Shuma. vlsid 2016: 493-498 [doi]

Practical statistical static timing analysis with current source modelsDebjit Sinha, Vladimir Zolotov, Sheshashayee K. Raghunathan, Michael H. Wood, Kerim Kalafala. dac 2016: 113 [doi]

Generation and use of statistical timing macro-models considering slew and load variabilityDebjit Sinha, Vladimir Zolotov, Jin Hu, Sheshashayee K. Raghunathan, Adil Bhanji, Christine M. Casey. iccad 2016: 98 [doi]

2014

TAU 2014 contest on removing common path pessimism during timing analysisJin Hu, Debjit Sinha, Igor Keller. iccad 2014: 591 [doi]

TAU 2014 contest on removing common path pessimism during timing analysisJin Hu, Debjit Sinha, Igor Keller. ispd 2014: 153-160 [doi]

2013

Speeding up computation of the max/min of a set of gaussians for statistical timing analysis and optimizationVimitha Kuruvilla, Debjit Sinha, Jeff Piaget, Chandu Visweswariah, Nitin Chandrachoodan. dac 2013: 182 [doi]

TAU 2013 variation aware timing analysis contestDebjit Sinha, Luís Guerra e Silva, Jia Wang, Shesha Raghunathan, Dileep Netrabile, Ahmed Shebaita. ispd 2013: 171-178 [doi]

2012

max/min operation: concept and applications to timingDebjit Sinha, Chandu Visweswariah, Natesan Venkateswaran, Jinjun Xiong, Vladimir Zolotov. dac 2012: 1067-1073 [doi]

Timing analysis with nonseparable statistical and deterministic variationsVladimir Zolotov, Debjit Sinha, Jeffrey G. Hemmett, Eric A. Foreman, Chandu Visweswariah, Jinjun Xiong, Jeremy Leitzen, Natesan Venkateswaran. dac 2012: 1061-1066 [doi]

2009

A Timing-Dependent Power Estimation Framework Considering CouplingDiaaEldin Khalil, Debjit Sinha, Hai Zhou, Yehea I. Ismail. tvlsi, 17(6):843-847, 2009. [doi]

Feasible Aggressor-Set Identification Under Constraints for Maximum Coupling NoiseDebjit Sinha, Alex Rubin, Chandu Visweswariah, Frank Borkam, Gregory Schaeffer, Soroush Abbaspour. tcad, 28(7):1096-1100, 2009. [doi]

2008

Driver waveform computation for timing analysis with multiple voltage threshold driver modelsPeter Feldmann, Soroush Abbaspour, Debjit Sinha, Gregory Schaeffer, Revanta Banerji, Hemlata Gupta. dac 2008: 425-428 [doi]

Constrained aggressor set selection for maximum coupling noiseDebjit Sinha, Gregory Schaeffer, Soroush Abbaspour, Alex Rubin, Frank Borkam. iccad 2008: 790-796 [doi]

2007

2006

Smart bit-width allocation for low power optimization in a systemc based ASIC design environmentArindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou. date 2006: 618-623 [doi]

Yield-Aware Cache ArchitecturesSerkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonathan Adams, Hai Zhou. micro 2006: 15-25 [doi]

Statistical Timing Yield Optimization by Gate SizingDebjit Sinha, Narendra V. Shenoy, Hai Zhou. tvlsi, 14(10):1140-1146, 2006. [doi]

Gate-size optimization under timing constraints for coupling-noise reductionDebjit Sinha, Hai Zhou. tcad, 25(6):1064-1074, 2006. [doi]

Statistical Timing Analysis With CouplingDebjit Sinha, Hai Zhou. tcad, 25(12):2965-2975, 2006. [doi]

A timing dependent power estimation framework considering couplingDebjit Sinha, DiaaEldin Khalil, Yehea I. Ismail, Hai Zhou. iccad 2006: 401-407 [doi]

Advances in Computation of the Maximum of a Set of Random VariablesDebjit Sinha, Hai Zhou, Narendra V. Shenoy. isqed 2006: 306-311 [doi]

2005

A unified framework for statistical timing analysis with coupling and multiple input switchingDebjit Sinha, Hai Zhou. iccad 2005: 837-843

Statistical gate sizing for timing yield optimizationDebjit Sinha, Narendra V. Shenoy, Hai Zhou. iccad 2005: 1037-1041

Yield driven gate sizing for coupling-noise reduction under uncertaintyDebjit Sinha, Hai Zhou. aspdac 2005: 192-197 [doi]

2004

An algorithm for trading off quantization error with hardware resources for MATLAB based FPGA designSanghamitra Roy, Debjit Sinha, Prithviraj Banerjee. fpga 2004: 256 [doi]

Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxationDebjit Sinha, Hai Zhou. iccad 2004: 14-19 [doi]

Optimal gate sizing for coupling-noise reductionDebjit Sinha, Hai Zhou, Chris C. N. Chu. ispd 2004: 176-181 [doi]

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