Abstract is missing.
- A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor DesignFayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee. 3-14 [doi]
- Yield-Aware Cache ArchitecturesSerkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonathan Adams, Hai Zhou. 15-25 [doi]
- Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable HardwareSmruti R. Sarangi, Abhishek Tiwari, Josep Torrellas. 26-37 [doi]
- PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug DetectionShan Lu, Pin Zhou, Wei Liu, Yuanyuan Zhou, Josep Torrellas. 38-52 [doi]
- Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed PathsHyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt. 53-64 [doi]
- Merging Head and Tail Duplication for Convergent Hyperblock FormationBertrand A. Maher, Aaron Smith, Doug Burger, Kathryn S. McKinley. 65-76 [doi]
- Data-Dependency Graph Transformations for Superblock SchedulingMark Heffernan, Kent D. Wilken, Ghassan Shobaki. 77-88 [doi]
- Dataflow PredicationAaron Smith, Ramadass Nagarajan, Karthikeyan Sankaralingam, Robert G. McDonald, Doug Burger, Stephen W. Keckler, Kathryn S. McKinley. 89-102 [doi]
- Authentication Control Point and Its Implications For Secure Processor DesignWeidong Shi, Hsien-Hsin S. Lee. 103-112 [doi]
- Using Branch Correlation to Identify Infeasible Paths for Anomaly DetectionXiaotong Zhuang, Tao Zhang, Santosh Pande. 113-122 [doi]
- Memory Protection through Dynamic Access ControlKun Zhang, Tao Zhang, Santosh Pande. 123-134 [doi]
- LIFT: A Low-Overhead Practical Information Flow Tracking System for Detecting Security AttacksFeng Qin, Cheng Wang, Zhenmin Li, Ho-Seop Kim, Yuanyuan Zhou, Youfeng Wu. 135-148 [doi]
- Fairness and Throughput in Switch on Event MultithreadingRon Gabor, Shlomo Weiss, Avi Mendelson. 149-160 [doi]
- A Predictive Performance Model for Superscalar ProcessorsP. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthaveetil. 161-170 [doi]
- Serialization-Aware Mini-Graphs: Performance with Fewer ResourcesAnne Bracy, Amir Roth. 171-184 [doi]
- Architectural Support for Software Transactional MemoryBratin Saha, Ali-Reza Adl-Tabatabai, Quinn Jacobson. 185-196 [doi]
- Virtually Pipelined Network MemoryBanit Agrawal, Timothy Sherwood. 197-207 [doi]
- Fair Queuing Memory SystemsKyle J. Nesbit, Nidhi Aggarwal, James Laudon, James E. Smith. 208-222 [doi]
- Reunion: Complexity-Effective Multicore RedundancyJared C. Smolens, Brian T. Gold, Babak Falsafi, James C. Hoe. 223-234 [doi]
- Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast BarriersJack Sampson, Rubén González, Jean-Francois Collard, Norman P. Jouppi, Michael S. Schlansker, Brad Calder. 235-246 [doi]
- CAPSULE: Hardware-Assisted Parallel Execution of Component-Based ProgramsPierre Palatin, Yves Lhuillier, Olivier Temam. 247-258 [doi]
- Support for High-Frequency Streaming in CMPsRam Rangan, Neil Vachharajani, Adam Stoler, Guilherme Ottoni, David I. August, George Z. N. Cai. 259-272 [doi]
- Fire-and-Forget: Load/Store Scheduling with No Store Queue at AllSamantika Subramaniam, Gabriel H. Loh. 273-284 [doi]
- NoSQ: Store-Load Communication without a Store QueueTingting Sha, Milo M. K. Martin, Amir Roth. 285-296 [doi]
- DMDC: Delayed Memory Dependence Checking through Age-Based FilteringFernando Castro, Luis Piñuel, Daniel Chaver, Manuel Prieto, Michael C. Huang, Francisco Tirado. 297-308 [doi]
- Coherence Ordering for Ring-based Chip MultiprocessorsMichael R. Marty, Mark D. Hill. 309-320 [doi]
- In-Network Cache CoherenceNoel Eisley, Li-Shiuan Peh, Li Shang. 321-332 [doi]
- ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip RoutersChrysostomos Nicopoulos, Dongkook Park, Jongman Kim, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das. 333-346 [doi]
- An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power BudgetCanturk Isci, Alper Buyuktosunoglu, Chen-Yong Cher, Pradip Bose, Margaret Martonosi. 347-358 [doi]
- Live, Runtime Phase Monitoring and Prediction on Real Systems with Application to Dynamic Power ManagementCanturk Isci, Gilberto Contreras, Margaret Martonosi. 359-370 [doi]
- Dynamic Standby Prediction for Leakage Tolerant Microprocessor Functional UnitsAhmed Youssef, Mohab Anis, Mohamed I. Elmasry. 371-384 [doi]
- Adaptive Caches: Effective Shaping of Cache Behavior to WorkloadsRanjith Subramanian, Yannis Smaragdakis, Gabriel H. Loh. 385-396 [doi]
- Memory Prefetching Using Adaptive Stream DetectionIbrahim Hur, Calvin Lin. 397-408 [doi]
- Scalable Cache Miss Handling for High Memory-Level ParallelismJames Tuck, Luis Ceze, Josep Torrellas. 409-422 [doi]
- Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared CachesMoinuddin K. Qureshi, Yale N. Patt. 423-432 [doi]
- Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regionsKeshavan Varadarajan, S. K. Nandy, Vishal Sharda, Amrutur Bharadwaj, Ravi R. Iyer, Srihari Makineni, Donald Newell. 433-442 [doi]
- ASR: Adaptive Selective Replication for CMP CachesBradford M. Beckmann, Michael R. Marty, David A. Wood. 443-454 [doi]
- Managing Distributed, Shared L2 Caches through OS-Level Page AllocationSangyeun Cho, Lei Jin. 455-468 [doi]
- Die Stacking (3D) MicroarchitectureBryan Black, Murali Annavaram, Ned Brekelbaum, John DeVale, Lei Jiang, Gabriel H. Loh, Don McCaule, Pat Morrow, Donald W. Nelson, Daniel Pantuso, Paul Reed, Jeff Rupley, Sadasivan Shankar, John Paul Shen, Clair Webb. 469-479 [doi]
- Distributed Microarchitectural Protocols in the TRIPS Prototype ProcessorKarthikeyan Sankaralingam, Ramadass Nagarajan, Robert G. McDonald, Rajagopalan Desikan, Saurabh Drolia, M. S. Govindan, Paul Gratz, Divya Gulati, Heather Hanson, Changkyu Kim, Haiming Liu, Nitya Ranganathan, Simha Sethumadhavan, Sadia Sharif, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger. 480-491 [doi]
- Leveraging Optical Technology in Future Bus-based Chip MultiprocessorsNevin Kirman, Meyrem Kirman, Rajeev K. Dokania, José F. Martínez, Alyssa B. Apsel, Matthew A. Watkins, David H. Albonesi. 492-503 [doi]
- Mitigating the Impact of Process Variations on Processor Register Files and Execution UnitsXiaoyao Liang, David Brooks. 504-514 [doi]