Abstract is missing.
- The four degrees of 3DRobert K. Montoye. 1 [doi]
- Almost optimum placement legalization by minimum cost flow and dynamic programmingUlrich Brenner, Anna Pauli, Jens Vygen. 2-9 [doi]
- Sensitivity guided net weighting for placement driven synthesisHaoxing Ren, David Zhigang Pan, David S. Kung. 10-17 [doi]
- Implementation and extensibility of an analytic placerAndrew B. Kahng, Qinke Wang. 18-25 [doi]
- FastPlace: efficient analytical placement using cell shifting, iterative local refinement and a hybrid net modelNatarajan Viswanathan, Chris C. N. Chu. 26-33 [doi]
- Multilevel routing with antenna avoidanceTsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen. 34-40 [doi]
- An ECO algorithm for eliminating crosstalk violationsHua Xiang, Kai-Yuan Chao, D. F. Wong. 41-46 [doi]
- A fast algorithm for identifying good buffer insertion candidate locationsCharles J. Alpert, Milos Hrkic, Stephen T. Quay. 47-52 [doi]
- Performance-driven register insertion in placementDennis K. Y. Tong, Evangeline F. Y. Young. 53-60 [doi]
- The great interconnect buffering debate: are you a chicken or an ostrich?Desmond Kirkpatrick, Peter J. Osler, Louis Scheffer, Prashant Saxena, Dennis Sylvester. 61 [doi]
- Floorplanning for throughputMario R. Casu, Luca Macchiarulo. 62-69 [doi]
- Multi-project reticle floorplanning and wafer dicingAndrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Xu Xu, Alexander Zelikovsky. 70-77 [doi]
- An area-optimality study of floorplanningJason Cong, Gabriele Nataneli, Michail Romesis, Joseph R. Shinnerl. 78-83 [doi]
- Recursive bisection based mixed block placementAteen Khatkhate, Chen Li 0004, Ameya R. Agnihotri, Mehmet Can Yildiz, Satoshi Ono, Cheng-Kok Koh, Patrick H. Madden. 84-89 [doi]
- Design methodology and tools for NEC electronics structured ASIC ISSPTakumi Okamoto, Tsutomu Kimoto, Naotaka Maeda. 90-96 [doi]
- Design considerations for regular fabricsDeepak D. Sherlekar. 97-102 [doi]
- Structured ASIC, evolution or revolution?Kun-Cheng Wu, Yu-Wen Tsai. 103-106 [doi]
- The four degrees of 3DRobert K. Montoye. 107 [doi]
- Technology, performance, and computer-aided design of three-dimensional integrated circuitsShamik Das, Andy Fan, Kuan-Neng Chen, Chuan Seng Tan, Nisha Checka, Rafael Reif. 108-115 [doi]
- Topology optimization of structured power/ground networksJaskirat Singh, Sachin S. Sapatnekar. 116-123 [doi]
- Sensitivity guided net weighting for placement driven synthesisTing-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen. 124-131 [doi]
- Early-stage power grid analysis for uncertain working modesHaifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar. 132-137 [doi]
- Power-aware clock tree planningMonica Donno, Enrico Macii, Luca Mazzoni. 138-147 [doi]
- Innovate or perish: FPGA physical designTaraneh Taghavi, Soheil Ghiasi, Abhishek Ranjan, Salil Raje, Majid Sarrafzadeh. 148-155 [doi]
- On optimal physical synthesis of sleep transistorsChangbo Long, Jinjun Xiong, Lei He. 156-161 [doi]
- Mutual inductance extraction and the dipole approximationRafael Escovar, Salvador Ortiz, Roberto Suaya. 162-169 [doi]
- A new multi-ramp driver model with RLC interconnect loadLakshmi Kalpana Vakati, Janet Meiling Wang. 170-175 [doi]
- Optimal gate sizing for coupling-noise reductionDebjit Sinha, Hai Zhou, Chris C. N. Chu. 176-181 [doi]
- Clock network sizing via sequential linear programming with time-domain analysisKai Wang, Malgorzata Marek-Sadowska. 182-189 [doi]
- Placement driven synthesis case studies on two sets of two chips: hierarchical and flatPeter J. Osler. 190-197 [doi]
- A study of netlist structure and placement efficiencyQinghua Liu, Malgorzata Marek-Sadowska. 198-203 [doi]
- Probabilistic congestion predictionJurjen Westra, Chris Bartels, Patrick Groeneveld. 204-209 [doi]
- A predictive distributed congestion metric and its application to technology mappingRupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang. 210-217 [doi]