D. F. Wong - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 100 from 162

2004

An ECO algorithm for eliminating crosstalk violationsHua Xiang, Kai-Yuan Chao, D. F. Wong. ispd 2004: 41-46 [doi]

2003

2002

Design hierarchy guided multilevel circuit partitioningYongseok Cheon, D. F. Wong. ispd 2002: 30-35 [doi]

Maze Routing with Buffer Insertion under Transition Time ConstraintsLi-Da Huang, Minghorng Lai, D. F. Wong, Youxin Gao. date 2002: 702-707 [doi]

A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna ProblemLi-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong, I-Min Liu. date 2002: 470-477 [doi]

Timing-driven routing for FPGAs based on Lagrangian relaxationSeokjin Lee, D. F. Wong. ispd 2002: 176-181 [doi]

Incremental reconfiguration of multi-FPGA systemsK. K. Lee, D. F. Wong. fpga 2002: 206-213 [doi]

Shaping interconnect for uniform current densityMuzhou Shao, D. F. Wong, Youxin Gao, Li-Pen Yuan, Huijing Cao. iccad 2002: 254-259 [doi]

Floorplanning with alignment and performance constraintsXiaoping Tang, D. F. Wong. dac 2002: 848-853 [doi]

On mask layout partitioning for electron projection lithographyRuiqi Tian, Ronggang Yu, Xiaoping Tang, D. F. Wong. iccad 2002: 514-518 [doi]

An algorithm for integrated pin assignment and buffer planningHua Xiang, D. F. Wong, Xiaoping Tang. dac 2002: 584-589 [doi]

ECO algorithms for removing overlaps between power rails and signal wiresHua Xiang, Kai-Yuan Chao, D. F. Wong. iccad 2002: 67-74 [doi]

2001

Faster and more accurate wiring evaluation in interconnect-centric floorplanningHung-Ming Chen, D. F. Wong, Wai-Kei Mak, Hannah Honghua Yang. glvlsi 2001: 62-67 [doi]

VLSI Circuit Performance Optimization by Geometric ProgrammingChris C. N. Chu, D. F. Wong. anor, 105(1-4):37-60, 2001. [doi]

Closed form solutions to simultaneous buffer insertion/sizing and wire sizingChris C. N. Chu, D. F. Wong. todaes, 6(3):343-371, 2001. [doi]

A graph based algorithm for optimal buffer insertion under accurate delay modelsYouxin Gao, D. F. Wong. date 2001: 535-539 [doi]

A fast and accurate delay estimation method for buffered interconnectsYouxin Gao, D. F. Wong. aspdac 2001: 533-538 [doi]

Memory-efficient interconnect optimizationMinghorng Lai, D. F. Wong. aspdac 2001: 198-202 [doi]

Slicing tree is a complete floorplan representationMinghorng Lai, D. F. Wong. date 2001: 228-232 [doi]

LRoute: a delay minimal router for hierarchical CPLDsK. K. Lee, D. F. Wong. fpga 2001: 12-20 [doi]

Integrated power supply planning and floorplanningI-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong. aspdac 2001: 589-594 [doi]

FAST-SP: a fast algorithm for block placement based on sequence pairXiaoping Tang, D. F. Wong. aspdac 2001: 521-526 [doi]

Network flow based buffer planningXiaoping Tang, D. F. Wong. integration, 30(2):143-155, 2001. [doi]

A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle ConstraintsXiaoping Tang, Ruiqi Tian, Hua Xiang, D. F. Wong. iccad 2001: 49-56 [doi]

Dummy feature placement for chemical-mechanical polishing uniformity in a shallow trench isolation processRuiqi Tian, Xiaoping Tang, D. F. Wong. ispd 2001: 118-123 [doi]

An Algorithm for Simultaneous Pin Assignment and RoutingHua Xiang, Xiaoping Tang, D. F. Wong. iccad 2001: 232 [doi]

2000

Timing-driven routing for symmetrical array-based FPGAsYao-Wen Chang, Kai Zhu, D. F. Wong. todaes, 5(3):433-450, 2000. [doi]

Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line ModelYouxin Gao, D. F. Wong. date 2000: 512 [doi]

Maze routing with buffer insertion and wiresizingMinghorng Lai, D. F. Wong. dac 2000: 374-378 [doi]

Meeting Delay Constraints in DSM by Minimal Repeater InsertionI-Min Liu, Adnan Aziz, D. F. Wong. date 2000: 436-440 [doi]

Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertionI-Min Liu, Tan-Li Chou, Adnan Aziz, D. F. Wong. ispd 2000: 33-38 [doi]

FPGA Partitioning with Complex Resource ConstraintsHuiqun Liu, Kai Zhu, D. F. Wong. vlsi, 2000(3):219-235, 2000. [doi]

A fast hypergraph min-cut algorithm for circuit partitioningWai-Kei Mak, D. F. Wong. integration, 30(1):1-11, 2000. [doi]

Planning buffer locations by network flowsXiaoping Tang, D. F. Wong. ispd 2000: 180-185 [doi]

Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence ComputationXiaoping Tang, D. F. Wong, Ruiqi Tian. date 2000: 106-111 [doi]

Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturabilityRuiqi Tian, D. F. Wong, Robert Boone. dac 2000: 667-670 [doi]

Optimal low power X OR gate decompositionHai Zhou, D. F. Wong. dac 2000: 104-107 [doi]

1999

Error Bounded Padé Approximation via Bilinear Conformal TransformationChung-Ping Chen, D. F. Wong. dac 1999: 7-12 [doi]

Integrated floorplanning and interconnect planningHung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani. iccad 1999: 354-357 [doi]

Shaping a VLSI wire to minimize Elmore delay with consideration of coupling capacitanceYouxin Gao, D. F. Wong. integration, 27(2):165-178, 1999. [doi]

Optimal Wire Shape with Consideration of Coupling Capacitance under Elmore Delay ModelYouxin Gao, D. F. Wong. aspdac 1999: 217-220 [doi]

An Exact Tree-Based Structural Technology Mapping Algorithm for Configurable Logic Blocks in FPGAsK. K. Lee, D. F. Wong. iccd 1999: 216-221 [doi]

Circuit Partitioning for Dynamically Reconfigurable FPGAsHuiqun Liu, D. F. Wong. fpga 1999: 187-194 [doi]

A graph theoretic optimal algorithm for schedule compression in time-multiplexed FPGA partitioningHuiqun Liu, D. F. Wong. iccad 1999: 400-405 [doi]

An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian RelaxationI-Min Liu, Adnan Aziz, D. F. Wong, Hai Zhou. iccd 1999: 210-215 [doi]

A fast hypergraph minimum cut algorithmWai-Kei Mak, D. F. Wong. iscas 1999: 170-173 [doi]

Advances in transistor timing, simulation, and optimization (tutorial abstract)Jacob White, Jacob Avidan, Abe Elfadel, D. F. Wong. iccad 1999: 611 [doi]

Generation of Universal Series-Parallel Boolean FunctionsFung Yu Young, Chris C. N. Chu, D. F. Wong. JACM, 46(3):416-435, 1999. [doi]

Slicing Floorplans with Boundary ConstraintFung Yu Young, D. F. Wong. aspdac 1999: 17-20 [doi]

Slicing floorplans with range constraintFung Yu Young, D. F. Wong. ispd 1999: 97-102 [doi]

Simultaneous Routing and Buffer Insertion with Restrictions on Buffer LocationsHai Zhou, D. F. Wong, I-Min Liu, Adnan Aziz. dac 1999: 96-99 [doi]

1998

Graph matching-based algorithms for FPGA segmentation designYao-Wen Chang, Jai-Ming Lin, D. F. Wong. iccad 1998: 34-39 [doi]

Fast and exact simultaneous gate and wire sizing by Lagrangian relaxationChung-Ping Chen, Chris C. N. Chu, D. F. Wong. iccad 1998: 617-624 [doi]

A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire SizingChris C. N. Chu, D. F. Wong. date 1998: 479 [doi]

Greedy wire-sizing is linear timeChris C. N. Chu, D. F. Wong. ispd 1998: 39-44 [doi]

Shaping a VLSI wire to minimize delay using transmission line modelYouxin Gao, D. F. Wong. iccad 1998: 611-616 [doi]

Exact Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTsMadhukar R. Korupolu, K. K. Lee, D. F. Wong. dac 1998: 708-711 [doi]

Network flow based circuit partitioning for time-multiplexed FPGAsHuiqun Liu, D. F. Wong. iccad 1998: 497-504 [doi]

Integrated partitioning and scheduling for hardware/software co-designHuiqun Liu, D. F. Wong. In ICCD. 1998: 609-614 [doi]

Circuit Partitioning with Complex Resource Constraints in FPGAsHuiqun Liu, Kai Zhu, D. F. Wong. fpga 1998: 77-84 [doi]

Performance-Driven Board-Level Routing for FPGA-Based Logic Emulation (Abstract)Wai-Kei Mak, D. F. Wong. fpga 1998: 260 [doi]

Performance-driven board-level routing for FPGA-based logic emulationWai-Kei Mak, D. F. Wong. In ICCD. 1998: 199-201 [doi]

Minimum Crosstalk Vertical Layer Assignment for Three-Layer VHV Channel RoutingShashidhar Thakur, Kai-Yuan Chao, D. F. Wong. vlsi, 1998(1):73-84, 1998. [doi]

Slicing floorplans with pre-placed modulesFung Yu Young, D. F. Wong. iccad 1998: 252-258 [doi]

Global Routing with Crosstalk ConstraintsHai Zhou, D. F. Wong. dac 1998: 374-377 [doi]

Optimal river routing with crosstalk constraintsHai Zhou, D. F. Wong. todaes, 3(3):496-514, 1998. [doi]

Timing-driven routing for symmetrical-array-based FPGAsKai Zhu, Yao-Wen Chang, D. F. Wong. In ICCD. 1998: 628-633 [doi]

1997

On retiming for FPGA logic module minimizationY. P. Chen, D. F. Wong. integration, 24(2):135-145, 1997. [doi]

A graph theoretic approach to feed-through pin assignmentY. P. Chen, D. F. Wong. integration, 24(2):147-158, 1997. [doi]

Optimal Wire-Sizing Function with Fringing Capacitance ConsiderationChung-Ping Chen, D. F. Wong. dac 1997: 604-607 [doi]

Closed form solution to simultaneous buffer insertion/sizing and wire sizingChris C. N. Chu, D. F. Wong. ispd 1997: 192-197 [doi]

A matrix synthesis approach to thermal placementChris C. N. Chu, D. F. Wong. ispd 1997: 163-168 [doi]

A new approach to simultaneous buffer insertion and wire sizingChris C. N. Chu, D. F. Wong. iccad 1997: 614-621 [doi]

A Fast And Accurate Technique To Optimize Characterization Tables For Logic SynthesisJohn F. Croix, D. F. Wong. dac 1997: 337-340 [doi]

Optimal shape function for a bi-directional wire under Elmore delay modelYouxin Gao, D. F. Wong. iccad 1997: 622-627 [doi]

Network flow based multi-way partitioning with area and pin constraintsHuiqun Liu, D. F. Wong. ispd 1997: 12-17 [doi]

Channel Segmentation Design for Symmentrical FPGAsWai-Kei Mak, D. F. Wong. iccd 1997: 496-501

Board-level multiterminal net routing for FPGA-based logic emulationWai-Kei Mak, D. F. Wong. todaes, 2(2):151-167, 1997. [doi]

Clustering and Load Balancing for Buffered Clock Tree SynthesisAshih D. Mehta, Yao-Ping Chen, Noel Menezes, D. F. Wong, Lawrence T. Pileggi. iccd 1997: 217-223

On the Construction of Universal Series-Parallel Functions for Logic Module DesignFung Yu Young, D. F. Wong. iccd 1997: 482-488

How good are slicing floorplans?F. Y. Young, D. F. Wong. integration, 23(1):61-73, 1997. [doi]

How good are slicing floorplans?Fung Yu Young, D. F. Wong. ispd 1997: 144-149 [doi]

An exact gate decomposition algorithm for low-power technology mappingHai Zhou, D. F. Wong. iccad 1997: 575-580 [doi]

Crosstalk-Constrained Maze Routing Based on Lagrangian RelaxationHai Zhou, D. F. Wong. iccd 1997: 628-633

1996

Universal Switch-Module Design for Symmetric-Array-Based FPGAsYao-Wen Chang, D. F. Wong, C. K. Wong. fpga 1996: 80-86 [doi]

Universal switch modules for FPGA designYao-Wen Chang, D. F. Wong, C. K. Wong. todaes, 1(1):80-101, 1996. [doi]

An Algorithm for Zero-Skew Clock Tree Routing with Buffer InsertionY. P. Chen, D. F. Wong. date 1996: 230-236 [doi]

Optimal Wire-Sizing Formular Under the Elmore Delay ModelChung-Ping Chen, Yao-Ping Chen, D. F. Wong. dac 1996: 487-490 [doi]

Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian RelaxationChung-Ping Chen, Yao-Wen Chang, D. F. Wong. dac 1996: 405-408 [doi]

Multiplexor Network Generation in High Level SynthesisYung-Ming Fang, D. F. Wong. iccd 1996: 78 [doi]

Minimum replication min-cut partitioningWai-Kei Mak, D. F. Wong. iccad 1996: 205-210 [doi]

Delay Minimal Decomposition of Multiplexers in Technology MappingShashidhar Thakur, D. F. Wong, Shankar Krishnamoorthy. dac 1996: 254-257 [doi]

Series-parallel functions and FPGA logic module designShashidhar Thakur, D. F. Wong. todaes, 1(1):102-122, 1996. [doi]

Universal Logic Modules for Series-Parallel FunctionsShashidhar Thakur, D. F. Wong. fpga 1996: 31-37 [doi]

Simultaneous area and delay minimum K-LUT mapping for K-exact networksShashidhar Thakur, D. F. Wong. integration, 20(3):287-302, 1996. [doi]

All Publications

Filter by Year
OR AND NOT 1

Filter by Type
OR AND NOT 1

Filter by Tag

[+]
OR AND NOT 1

Filter by Venue
OR AND NOT 1

Filter by Author

[+]
OR AND NOT 1

Filter by Top Terms

[+]
OR AND NOT 1

Researchr

Publications by 'D. F. Wong'

Viewing Publication 1 - 100 from 162

2004

2003

2002

2001

2000

1999

1998

1997

1996

All Publications

Filter by YearOR AND NOT 1

Filter by TypeOR AND NOT 1

Filter by Tag [+]OR AND NOT 1

Filter by VenueOR AND NOT 1

Filter by Author [+]OR AND NOT 1

Filter by Top Terms [+]OR AND NOT 1

Researchr

Publications by 'D. F. Wong'

Viewing Publication 1 - 100 from 162

2004

2003

2002

2001

2000

1999

1998

1997

1996

Filter by Year
OR AND NOT 1

Filter by Type
OR AND NOT 1

Filter by Tag

[+]
OR AND NOT 1

Filter by Venue
OR AND NOT 1

Filter by Author

[+]
OR AND NOT 1

Filter by Top Terms

[+]
OR AND NOT 1