Abstract is missing.
- Requirements for models of achievable routingAndrew B. Kahng, Stefanus Mantik, Dirk Stroobandt. 4-11 [doi]
- DUNE: a multi-layer gridless routing system with wire planningJason Cong, Jie Fang, Kei-Yong Khoo. 12-18 [doi]
- Provably good global routing by a new approximation algorithm for multicommodity flowChristoph Albrecht. 19-25 [doi]
- Exact switchbox routing with search space reductionFrank Schmiedle, Daniel Unruh, Bernd Becker. 26-32 [doi]
- Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertionI-Min Liu, Tan-Li Chou, Adnan Aziz, D. F. Wong. 33-38 [doi]
- The bottom-10 problems in EDA (panel session (title only))Naveed A. Sherwani. 39 [doi]
- Pseudo pin assignment with crosstalk noise controlChin-Chih Chang, Jason Cong. 41-47 [doi]
- Aggressor alignment for worst-case coupling noiseLauren Hui Chen, Malgorzata Marek-Sadowska. 48-54 [doi]
- Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimizationLei He, Kevin M. Lepak. 55-60 [doi]
- A two moment RC delay metric for performance optimizationCharles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap. 69-74 [doi]
- Layout tools for analog ICs and mixed-signal SoCs: a surveyRob A. Rutenbar, John M. Cohn. 76-83 [doi]
- Incremental physical designJason Cong, Majid Sarrafzadeh. 84-92 [doi]
- Itanium processor clock designUtpal Desai, Simon Tam, Robert Kim, Ji Zhang, Stefan Rusu. 94-98 [doi]
- Methodology for repeater insertion management in the RTL, layout, floorplan and fullchip timing databases of the Itanium microprocessorRory McInerney, Kurt Leeper, Troy Hill, Heming Chan, Bulent Basaran, Lance McQuiddy. 99-104 [doi]
- Buffer minimization in pass transistor logicHai Zhou, Adnan Aziz. 105-110 [doi]
- A performance optimization method by gate sizing using statistical static timing analysisMasanori Hashimoto, Hidetoshi Onodera. 111-116 [doi]
- Simulating frequency-dependent current distribution for inductance modeling of on-chip copper interconnectsLi-Fu Chang, Keh-Jeng Chang, Robert Mathews. 117-120 [doi]
- Optimal reliable crosstalk-driven interconnect optimizationIris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou. 128-133 [doi]
- Critical area computation for missing material defects in VLSI circuitsEvanthia Papadopoulou. 140-146 [doi]
- Multi-center congestion estimation and minimization during placementMaogang Wang, Xiaojian Yang, Kenneth Eguro, Majid Sarrafzadeh. 147-152 [doi]
- A snap-on placement toolXiaojian Yang, Maogang Wang, Kenneth Eguro, Majid Sarrafzadeh. 153-158 [doi]
- A practical clock tree synthesis for semi-synchronous circuitsMasahiko Toyonaga, Keiichi Kurokawa, Takuya Yasui, Atsushi Takahashi. 159-164 [doi]
- EDA and the Internet (panel session - title only)D. Hill, Mark Gilbreath, Wayne Heideman, J. George Janac, Adriaan Ligtenberg. 165 [doi]
- An enhanced perturbing algorithm for floorplan design using the O-tree representationYingxin Pang, Chung-Kuan Cheng, Takeshi Yoshimura. 168-173 [doi]
- Floorplan area minimization using Lagrangian relaxationFung Yu Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong. 174-179 [doi]
- Planning buffer locations by network flowsXiaoping Tang, D. F. Wong. 180-185 [doi]
- Routability-driven repeater block planning for interconnect-centric floorplanningProbir Sarkar, Vivek Sundararaman, Cheng-Kok Koh. 186-191 [doi]
- Multilevel cooperative search: application to the circuit/hypergraph partitioning problemMin Ouyang, Michel Toulouse, Krishnaiyan Thulasiraman, Fred Glover, Jitender S. Deogun. 192-198 [doi]
- What is a floorplan?Ralph H. J. M. Otten. 201-206 [doi]
- Classical floorplanning harmful?Andrew B. Kahng. 207-213 [doi]
- The right floorplanning formulations for future chip implementation methodologies (panel discussion - title only)Patrick Groeneveld, Jacob Greidinger, J. George Janac, Wilm E. Donath. 214 [doi]