Bulent Basaran - researchr alias

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Viewing Publication 1 - 8 from 8

2022

Determining the perceptions of pre-service teachers on technology-based learning during the Covid-19 process: a latent class analysis approachBulent Basaran, Murat Yalman. eait, 27(6):7471-7490, 2022. [doi]

2021

Examining PRESERVICE teachers' use of SMARTBOARD and pc tablets in lessonsMurat Yalman, Bulent Basaran. eait, 26(2):1435-1453, 2021. [doi]

2018

Analog Placement Constraint Extraction and Exploration with the Application to Layout RetargetingBiying Xu, Bulent Basaran, Ming Su, David Z. Pan. ispd 2018: 98-105 [doi]

2009

Accelerated design of analog, mixed-signal circuits in TitanAnirudh Devgan, Bulent Basaran, David Colleran, Mar Hershenson. ispd 2009: 67-72 [doi]

2000

Methodology for repeater insertion management in the RTL, layout, floorplan and fullchip timing databases of the Itanium microprocessorRory McInerney, Kurt Leeper, Troy Hill, Heming Chan, Bulent Basaran, Lance McQuiddy. ispd 2000: 99-104 [doi]

1999

GeneSys: A Leaf-Cell Layout Synthesis System for GHz VLSI DesignsBulent Basaran, Kiran Ganesh, Raymond Y. K. Lau, Artour Levin, Miles McCoo, Srinivasan Rangarajan, Naresh Sehgal. vlsid 1999: 448-452 [doi]

1996

An ::::O(n):::: Algorithm for Transistor Stacking with Performance ConstraintsBulent Basaran, Rob A. Rutenbar. dac 1996: 221-226 [doi]

1993

Latchup-aware placement and parasitic-bounded routing of custom analog cellsBulent Basaran, Rob A. Rutenbar, L. Richard Carley. iccad 1993: 415-421 [doi]

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