Abstract is missing.
- Invited Talk: The Information Appliance and Its Interface to the Analog World: Easy - Or Not So EasyRobert A. Pease.
- Invited Talk: Practical Use of Formal Verification - Where are we? Where do we go?Ramayya Kumar.
- Invited Talk: Embedded Test for Systems-on-a-ChipVinod K. Agarwal.
- Mini-Tutorial: Bridging the Gap between TCAD and ECAD Methodologies in Deep Sub-Micron Interconnect Extraction and AnalysisNagaraj Ns, Poras T. Balsara, Cyrus D. Cantrell. 6-11
- Incorporating Process Induced Effects into RC ExtractionLi-Fu Chang, Abhay Dubey, Keh-Jeng Chang, Robert Mathews, Ken Wong. 12-17
- A New Methodology for Concurrent Technology Development and Cell Library OptimizationMarko P. Chew, Sharad Saxena, Thomas F. Cobourn, Purnendu K. Mozumder, Andrzej J. Strojwas. 18-25 [doi]
- A Low-Power Digital Camera-on-a-Chip Implemented in CMOS Active Pixel ApproachBedabrata Pain, Guang Yang, Brita Olson, Timothy Shaw, Monico Ortiz, Julie Heynssens, Chris Wrigley, Charlie Ho. 26-31 [doi]
- A Low-Power Wireless Camera SystemAnantha Chandrakasan, Abram P. Dancy, James Goodman, Thomas Simon. 32-36
- Assignment and Reordering of Incompletely Specified Pattern Sequences Targetting Minimum Power DissipationPaulo F. Flores, José C. Costa, Horácio C. Neto, José C. Monteiro, João P. Marques Silva. 37-41 [doi]
- Low Power Code Generation of Multiplication-free Linear TransformsMahesh Mehendale, Sunil D. Sherlekar. 42-47
- Automatic Insertion of Gated Clocks at Register Transfer LevelNithya Raghavan, Venkatesh Akella, Smita Bakshi. 48-54 [doi]
- Compact, Ultra Low Power, Programmable Continuous-Time Filter Banks for Feedback Cancellation in Hearing AidKavita Nair, Ramesh Harjani. 55-60 [doi]
- A Low-Complexity, Reduced-Power Viterbi AlgorithmP. K. Singh, Sriram Jayasimha. 61-66
- A Low Power 256 KB SRAM DesignBasabi Bhaumik, Pravas Pradhan, G. S. Visweswaran, Rajamohan Varambally, Anand Hardi. 67-71
- Efficient Techniques for Reducing IDDQ Observation Time for Sequential CircuitsYoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita. 72-77
- IDDQ-Testability of Tree CircuitsR. D. (Shawn) Blanton. 78-86 [doi]
- Test-Vector Prediction of M-Testable Iterative ArraysM. Jamoussi. 87-90
- A Comparative Study of Pseudo Stuck-At and Leakage Fault ModelSujit T. Zachariah, Sreejit Chakravarty. 91-94
- A New Test Compression SchemeBasabi Bhaumik, G. S. Visweswaran, R. Lakshminarasimhan. 95-99
- Mini-Tutorial: IC Layout and Manufacturability: Critical Links and Design Flow ImplicationsAndrew B. Kahng. 100-105
- New and Exact Filling Algorithms for Layout Density ControlAndrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky. 106-110
- Design for Manufacturing in the Semiconductor Industry: The Litho/Design WorkshopsFranklin M. Schellenberg. 111-119
- Interconnect Simple, Accurate and Statistical Models Using On-Chip Measurements for CalibrationAkis Doganis, James C. Chen. 120-127
- MPEG-2 Video Data Simulator: A Case Study in Constrained HW-SW CodesignRashmi Goswami, V. Srinivasan, M. Balakrishnan. 128-132 [doi]
- Processor Modeling for Hardware Software CodesignV. Rajesh, Rajat Moona. 132-137
- Synthesis of DMA Controllers from Architecture Independent Descriptions of HW/SW Communication ProtocolsMattias O Nils, Axel Jantsch. 138-145 [doi]
- Hierarchical Conditional Dependency Graphs for Mutual Exclusiveness IdentificationApostolos A. Kountouris, Christophe Wolinski. 146-150 [doi]
- Formal Analysis of Single WAIT VHDL processes for Semantic Based SynthesisLudovic Jacomme, Frédéric Pétrot, Rajesh K. Bawa. 151-156 [doi]
- nvited Talk: Micro-2010: Lead Microprocessor for 2010 - Myth or Reality?Manpreet S. Khaira. 157-159
- Exact Output Response Computation of RC Interconnects under Polynomial Input WaveformsSatrajit Gupta, Lalit M. Patnaik. 160-163 [doi]
- Sub-Circuit Analysis for Power Supply Rejection Ratio in Regulated Cascode Operational Transconductance Amplifiers and FiltersA. B. Bhattacharyya, Saudas Dey. 164-168
- Efficient DC Analysis of RVJ Circuits for Moment and Derivative Commutations of Interconnect NetworksShabbir H. Batterywala, H. Narayanan. 169-174
- A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing AnalysisSavithri Sundareswaran, David Blaauw, Abhijit Dharchoudhury. 175-180 [doi]
- Timed Circuit Synthesis Using Implicit MethodsRobert Thacker, Wendy Belluomini, Chris J. Myers. 181-188 [doi]
- A New Approach for CMOS Op-Amp SynthesisPradip Mandal, V. Visvanathan. 189-195
- Multi-Valued Logic SynthesisRobert K. Brayton, Sunil P. Khatri. 196-105
- Sequential Multi-Valued Network Simplification using Redundancy RemovalSunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 206-211 [doi]
- Residue Arithmetic Multiplier Based on the Radix-4 Signed-Digit Multiple-Valued Arithmetic CircuitsShugang Wei, Kensuke Shimizu. 212-217
- Functional Decomposition through Structural Analysis of Decision Diagrams - the Binary and Multiple-Valued CasesLuca Macchiarulo, Pierluigi Civera. 218
- Controlling State Explosion in Static Simulation by Selective CompositionPartha Pratim Chakrabarti, Pallab Dasgupta, Partha Pratim Das, Arnob Roy, Shuvendu K. Lahiri, Mrinal Bose. 226-231 [doi]
- FzCRITIC - A Functional Timing Verifier Using a Novel Fuzzy Delay ModelRathish Jayabharathi, Manuel A. d Abreu, Jacob A. Abraham. 232-235
- Efficient Simulation for Hierarchical and Partitioned CircuitsPeter M. Maurer. 236-241 [doi]
- Simulation and Modeling of a Multicast ATM SwitchAjoy C. Siddabathuni, M. Balakrishnan. 242
- VERSE: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential CircuitsIrith Pomeranz, Sudhakar M. Reddy. 250-255 [doi]
- Study of Correlation of Testability Aspects of RTL Description and Resulting Structural ImplementationsPradip A. Thaker, Mona E. Zaghloul, Minesh B. Amin. 256-259 [doi]
- An Approach to Evaluating the Effects of Realistic Faults in Digital CircuitsZbigniew Kalbarczyk, Janak H. Patel, Myeong S. Lee, Ravishankar K. Iyer. 260-265
- A Low Cost Approach for Detecting, Locating, and Avoiding Interconnect Faults in FPGA-Based Reconfigurable SystemsDebaleena Das, Nur A. Touba. 266-269 [doi]
- Design and Test of MEMsBernard Courtois, Jean-Michel Karam, Salvador Mir, Marcelo Lubaszewski, Vladimir Székely, Márta Rencz, Klaus Hofmann, Manfred Glesner. 270
- Formal Verification of an ARM ProcessorVishnu A. Patankar, Alok Jain, Randal E. Bryant. 282-287 [doi]
- Formal Verification of a Snoop-Based Cache Coherence Protocol Using Symbolic Model CheckingSrivatsan Srinivasan, Parminder Singh Chhabra, Praveen Kumar Jaini, Adnan Aziz, Lizy Kurian John. 288-293 [doi]
- An Efficiently Checkable Subset of TCTL for Formal Verification of Transition Systems with DelaysJatindra Kumar Deka, Pallab Dasgupta, P. P. Chakrabarti. 294-299 [doi]
- Superscalar Processor Validation at the Microarchitecture LevelNoppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen. 300-305 [doi]
- Verifying Tomasulo s Algoithm by RefinementTamarah Arons, Amir Pnueli. 306-309 [doi]
- Logic Verification of Very Large Circuits Using SharkJeremy Casas, Hannah Honghua Yang, Manpreet Khaira, Mandar Joshi, Thomas Tetzlaff, Steve W. Otto, Erik Seligman. 310-317 [doi]
- Formal System Design Based on the Synchrony Hypothesis, Functional Models and SkeletonsIngo Sander, Axel Jantsch. 318-323
- Exploiting Isomorphism for Compaction and Faster Simulation of Binary Decision DiagramsPankaj Chauhan, Pallab Dasgupta, P. P. Chakrabarti. 324 [doi]
- Array Index Allocation under Register Constraints in DSP ProgramsAnupam Basu, Rainer Leupers, Peter Marwedel. 330-335
- Parallel Implementation of 2D-Discrete Cosine Transform Using EPLDsD. V. R. Murthy, S. Ramachandran, S. Srinivasan. 336-339 [doi]
- Improving Area Efficiency of Residue Number System based Implementation of DSP AlgorithmsM. N. Mahesh, Satrajit Gupta, Mahesh Mehendale. 340-345 [doi]
- A Design-in Methodology to Ensure First Time Success of Complex Digital Signal ProcessorsAvinash K. Gautam, Jagdish C. Rao, Rohit Rathi, H. Udayakumar. 346-349 [doi]
- Synthesis of Configurable Architectures for DSP AlgorithmsS. Ramanathan, V. Visvanathan, S. K. Nandy. 350-357 [doi]
- Analytical Expressions for Power Dissipation of Macro-blocks in DSP ArchitecturesSudhakar Bobba, Ibrahim N. Hajj, Naresh R. Shanbhag. 358 [doi]
- Optimal Retiming for Initial State ComputationPeichen Pan, Guohua Chen. 366-371 [doi]
- Performance Driven Synthesis for Pass-Transistor LogicTai-Hung Liu, Malay K. Ganai, Adnan Aziz, Jeffrey L. Burns. 372-377
- A State Assignment Scheme Targeting Performance and AreaB. N. V. Malleswara Gupta, H. Narayanan, Madhav P. Desai. 378-383 [doi]
- Efficient Translation of Statecharts to Hardware CircuitsS. Ramesh. 384-389 [doi]
- Heuristic Technology Mapper For Lut Based FpgasChitrasena Bhat, Niranjan N. Chiplunkar. 390-393 [doi]
- Efficient Scheduling Techniques for ROBDD ConstructionRajeev Murgai, Jawahar Jain, Masahiro Fujita. 394-401 [doi]
- The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive LatchesPrashant Saxena, Peichen Pan, C. L. Liu. 402-407 [doi]
- Recent Advances in BDD Based Representations for Boolean Functions: A SurveyAmit Narayon. 408 [doi]
- POWERTEST: A Tool for Energy Conscious Weighted Random Pattern TestingXiaodong Zhang, Kaushik Roy, Sudipta Bhawmik. 416-422
- Simultaneous Scheduling, Binding and Floorplanning for Interconnect Power OptimizationPradeep Prabhakaran, Prithviraj Banerjee, Jim E. Crenshaw, Majid Sarrafzadeh. 423-427 [doi]
- Optimal Voltages and Sizing for Low PowerMircea R. Stan. 428-433 [doi]
- Digital Circuit Design for Minimum Transient Energy and a Linear Programming MethodVishwani D. Agrawal, Michael L. Bushnell, Ganapathy Parthasarathy, Rajesh Ramadoss. 434-439 [doi]
- Energy Efficient Datapath Synthesis Using Dynamic Frequency Clocking and Multiple VoltagesVamsi Krishna, N. Ranganathan, Narayanan Vijaykrishnan. 440 [doi]
- GeneSys: A Leaf-Cell Layout Synthesis System for GHz VLSI DesignsBulent Basaran, Kiran Ganesh, Raymond Y. K. Lau, Artour Levin, Miles McCoo, Srinivasan Rangarajan, Naresh Sehgal. 448-452 [doi]
- Near-Optimum Hierarchical Layout Synthesis of Two-Dimensional CMOS CellsAvaneendra Gupta, John P. Hayes. 453-459 [doi]
- COST Circuit Optimization SysTem in ASIC Library Development EnvironmentC. S. Raghu, Suravi Bhowmik, Poorvaja Ramani, S. Sundaram. 460-463 [doi]
- Interconnect Optimization Strategies for High-Performance VLSI DesignsAndrew B. Kahng, Sudhakar Muddu, Egino Sarto. 464-469
- Modeling Crosstalk in Resistive VLSI InterconnectionsAshok Vittal, Lauren Hui Chen, Malgorzata Marek-Sadowska, Kai-Ping Wang, Sherry Yang. 470-475 [doi]
- Spec-Based Repeater Insertion and Wire Sizing for On-chip InterconnectNoel Menezes, Chung-Ping Chen. 476 [doi]
- A Test Generator for Segment Delay FaultsKeerthi Heragu, Janak H. Patel, Vishwani D. Agrawal. 484-491 [doi]
- A Complete Characterization of Path Delay Faults through Stuck-at FaultsSubhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell. 492-497 [doi]
- A Diagnostic Fault Simulator for Fast Diagnosis of Bridge FaultsJue Wu, Elizabeth M. Rudnick. 498-505 [doi]
- Empirical Computation of Reject Ratio in VLSI TestingShashank K. Mehta, Sharad C. Seth. 506-511 [doi]
- Synthesis of Symmetric Functions for Path-Delay Fault TestabilitySusanta Chakraborty, Sandip Das, Debesh K. Das, Bhargab B. Bhattacharya. 512-517 [doi]
- Diagnostic Test Pattern Generation for Analog Circuits Using Hierarchical ModelsSudip Chakrabarti, Abhijit Chatterjee. 518-523 [doi]
- Design Considerations and Implementation of a High Performance Dynamic Register FileRajiv V. Joshi, Wei Hwang. 526-531 [doi]
- A VLSI Architecture for On-Line Image Decompression Using GF(28) Cellular AutomataKolin Paul, Paramartha Dutta, Dipanwita Roy Chowdhury, Prasanta Kumar Nandi, Parimal Pal Chaudhuri. 532-537
- Lossy Compression of Images Using Logic MinimizationJacob Augustine, William E. Lynch, Yuke Wang, Asim J. Al-Khalili. 538-543 [doi]
- Design, Simulation and Synthesis of an ASIC for Fractal Image CompressionSwarup Bhunia, Soumya K. Ghosh, Pramod Kumar, Partha Pratim Das, Jayanta Mukherjee. 544-547 [doi]
- Invited Talk: Quantum ComputationLov K. Grover. 548
- FAAR: A Router for Field-Programmable Analog ArraysSree Ganesan, Ranga Vemuri. 556-563
- High Performance MCM Routing: A New ApproachSandip Das, Subhas C. Nandy, Bhargab B. Bhattacharya. 564-569 [doi]
- Sequential Chaotic Annealing and its Application to Multilayer Channel RoutingJayadeva. 570-573 [doi]
- Satisfiability-Based Detailed FPGA RoutingGi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar. 574-577 [doi]
- Improved Effective Capacitance Computations for Use in Logic and Layout OptimizationAndrew B. Kahng, Sudhakar Muddu. 578-583 [doi]
- A Semi-Digital Delay Locked Loop for Clock Skew MinimizationJoonbae Park, Yido Koo, Wonchan Kim. 584-588 [doi]
- Component Characterization and Constraint Transformation Based on Directed Intervals for Analog SynthesisNagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri. 589-596
- Test Generation for Analog Circuits Using Partial Numerical SimulationPramodchandran N. Variyam, Junwei Hou, Abhijit Chatterjee. 597-602 [doi]
- Silicon-Level Physical Verification of Sub Wavelength(tm) DesignsFang-Cheng Chang, Melissa Kwok, Kenneth Rachlin, Robert Pack. 603
- Manufacturability of Mixed Signal SystemsManuel d Arbreu, Abhijit Chatterjee. 608
- CAD Techniques for Embedded System DesignSrinivas Devadas, Sharad Malik, José C. Monteiro, Luciano Lavagno. 608
- Low Power Design Methodologies for Systems-on-ChipsKaushik Roy, Anand Raghunathan, Sujit Dey. 609
- Built-In Self-Test for Systems on SiliconJanusz Rajski, Jerzy Tyszer, Sanjay Patel. 609-610
- VLSI Signal Processing in FPGAsSudip Nag, H. K. Verma, Kaushik Roy. 609
- Verification of Systems-on-Chip DesignsRahul Razdan, Apurva Kalia, Manu Lauria. 609
- Design and Implementation of Viterbi Decoder Using FPGAsBupesh Pandita, Subir K. Roy. 611 [doi]
- TECHMIG: A Layout Tool for Technology MigrationPradip K. Kar, Subir K. Roy. 615-620 [doi]
- Analyzing Forced Oscillators with Multiple Time ScalesOnuttom Narayan, Jaijeet S. Roychowdhury. 621 [doi]
- Characterizing Individual Gate Power Sensitivity in Low Power DesignUnni Narayanan, Georgios I. Stamoulis, Rabindra K. Roy. 625
- Improving the Diagnosability of Digital CircuitsC. P. Ravikumar, Manish Sharma, R. K. Patney. 629-634
- Hierarchical Delay Fault SimulationC. P. Ravikumar, Ajay Mittal. 635 [doi]