Sunil D. Sherlekar - researchr alias

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Viewing Publication 1 - 27 from 27

2012

Parallel Computing Goes MainstreamSunil D. Sherlekar. ic3 2012: 4-5 [doi]

Intel Many Integrated Core (MIC) ArchitectureSunil D. Sherlekar. icpads 2012: 947 [doi]

2003

A Global Access Independent Billing Model: Users' PerspectiveSunil D. Sherlekar, Rajeev Prasad. wpc, 26(2-3):169-178, 2003. [doi]

2000

Power Reduction Techniques for Portable DSP ApplicationsMahesh Mehendale, Sunil D. Sherlekar. vlsid 2000: 3

1999

Low Power Code Generation of Multiplication-free Linear TransformsMahesh Mehendale, Sunil D. Sherlekar. vlsid 1999: 42-47

1998

1997

Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR FiltersMahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh. vlsid 1997: 124-129 [doi]

1996

Optimized Code Generation of Multiplication-free Linear TransformsMahesh Mehendale, G. Venkatesh, Sunil D. Sherlekar. dac 1996: 41-46 [doi]

Low power realization of FIR filters using multirate architecturesMahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh. vlsid 1996: 370-375 [doi]

Monitoring machine based synthesis technique for concurrent error detection in finite state machinesRubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar. et, 8(2):179-201, 1996. [doi]

1995

1993

State Assignment for Optimal Design of Monitored Self-Checking Sequential CircuitsRubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar. vlsid 1993: 15-20

Export of VLSI Design and CAD: Present and FutureSunil D. Sherlekar. vlsid 1993: 264

1992

A Behavioral Fault Simulator for IdealAjay Khoche, Sunil D. Sherlekar, G. Venkatesh, Raja Venkateswaran. dt, 9(4):14-21, 1992. [doi]

A Behavioral Fault Simulator For IdealAjay Khoche, Sunil D. Sherlekar, G. Venkatesh. vlsid 1992: 137-143 [doi]

Path breaker: a tool for the optimal design of speed independent asynchronous controllersYogesh Mishra, Sunil D. Sherlekar, G. Venkatesh. eurodac 1992: 2-8 [doi]

1991

A methodology for the design of SFS/SCD circuits for a class of unordered codesSandeep Pagey, Sunil D. Sherlekar, G. Venkatesh. et, 2(3):261-277, 1991. [doi]

A Methodology for Designing Optimal Self-Checking Sequential CircuitsRubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar. itc 1991: 283-291

1989

Ideas: a tool for VLSI CADAlok Kumar, Vijeta Kashyap, Sunil D. Sherlekar, G. Venkatesh 0001, S. Biswas, Anshul Kumar, P. C. P. Bhatt, Sashi Kumar. dt, 6(5):50-57, 1989. [doi]

1988

Conditionally robust two-pattern tests and CMOS design for testabilitySunil D. Sherlekar, P. S. Subramanian. tcad, 7(3):325-332, 1988. [doi]

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