Table of Contents

• T1: MultimediaK. R. Rao, Magdy A. Bayoumi, T. V. Subramaniam. 2 [doi]
• T2: HW-SW CodesignP. A. Subrahmanyam, R. Gupta, B. S. Rao. 2 [doi]
• T3: Physical DesignDinesh P. Mehta, Naveed A. Sherwani, A. Bariya. 3 [doi]
• T4: VerificationR. Raina, Jacob A. Abraham, A. K. Pujari. 3 [doi]
• T5: Low-Power DesignK. Roy, R. Roy, Ramesh Harjani, K. S. Murthy. 4 [doi]
• T6: C++/java(Tm)/unixP. Meyer. 4 [doi]
• Opto-VLSI Systems for Multimedia ComputingKamran Eshraghian. 6-9 [doi]
• Parallel VLSI-Routing Models for Polymorphic Processors ArrayP. Mazumdar. 10-14 [doi]
• A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS CellsAvaneendra Gupta, John P. Hayes. 15-20
• Macro Block Based FPGA FloorplanningJianzhong Shi, Akash Randhar, Dinesh Bhatia. 21-26 [doi]
• Channel and Switchbox Routing with Minimized Crosstalk - A Parallel Genetic Algorithm ApproachJens Lienig. 27-31 [doi]
• A New Partitioning Strategy Based on Supermodular FunctionsSachin B. Patkar, Shabbir H. Batterywala, M. Chandramouli, H. Narayanan. 32-37 [doi]
• Effective Heuristics for Timing Driven Constructive PlacementR. V. Raj, N. S. Murty, P. S. Nagendra Rao, Lalit M. Patnaik. 38-45 [doi]
• Decision Diagrams in Synthesis - Algorithms, Applications and ExtensionsBernd Becker, Rolf Drechsler. 46-50 [doi]
• An Enhanced Genetic Solution for Scheduling, Module Allocation, and Binding in VLSI DesignGary William Grewal, Thomas Charles Wilson. 51-56 [doi]
• A Technology Mapper for Xilinx FPGAsMadhav Y. Chikodikar, Shridhar Laddha, Ashish Sirasao. 57-61 [doi]
• Rapid Synthesis of Multi-Chip SystemsDong-Hyun Heo, Alice C. Parker, C. P. Ravikumar. 62-68 [doi]
• Simulated Annealing Based Parallel State Assignment of Finite State MachinesGagan Hasteer, Prithviraj Banerjee. 69-75 [doi]
• Synthesis for Logical Initializability of Synchronous Finite State MachinesMontek Singh, Steven M. Nowick. 76-81 [doi]
• A Method for Identifying Robust Dependent and Functionally Unsensitizable PathsSeiji Kajihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy. 82-87 [doi]
• Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test GenerationMandyam-Komar Srinivas, Michael L. Bushnell, Vishwani D. Agrawal. 88-94 [doi]
• Primitive Path Delay Fault IdentificationMukund Sivaraman, Andrzej J. Strojwas. 95-100 [doi]
• (Quasi-) Linear Path Delay Fault Tests for AddersBernd Becker, Rolf Drechsler, Sudhakar M. Reddy. 101-105 [doi]
• Delay Fault Coverage Enhancement Using Multiple Test Observation TimesWen-Ben Jone, Yun-Pan Ho, Sunil R. Das. 106-110 [doi]
• Analytical Fast Timing Simulation of MOS Circuits Driving RC InterconnectsA. Dharchoudhuri, S. M. Kang. 111-117 [doi]
• A Graph-Theoretic Approach for Register File Based SynthesisC. P. Ravikumar, R. Aggarwal, C. Sharma. 118-123 [doi]
• Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR FiltersMahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh. 124-129 [doi]
• Allocation of FIFO Structures in RTL Data PathsHeman Khanna, M. Balakrishnan. 130-133 [doi]
• Optimal Clock Period for Synthesized Data PathsA. R. Naseer, M. Balakrishnan, Anshul Kumar. 134-139 [doi]
• Resource Constrained RTL Partitioning for Synthesis of Multi-FPGA DesignsMadhavi Vootukuru, Ranga Vemuri, Nand Kumar. 140-145 [doi]
• Hardware/Software Co-Design for Data-Driven Xputer-based AcceleratorsReiner W. Hartenstein, Jürgen Becker. 146-150 [doi]
• Analyzing Controllability of a Hardware Circuit for its ReuseSantonu Sarkar, Anupam Basu, Arun K. Majumdar. 151-154 [doi]
• Hardware Software Partitioning Using Genetic AlgorithmDebanjan Saha, Anupam Basu, Raj S. Mitra. 155-160 [doi]
• Formal Techniques for Hardware AllocationJosé M. Mendías, Román Hermida, Milagros Fernández. 161-165 [doi]
• Design Space Exploration for Data Path SynthesisChittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose. 166-173 [doi]
• Algorithms for Low Power FIR Filter Realization Using Differential CoefficientsNaushik Sankarayya, Kaushik Roy, Debashis Bhattacharya. 174-178 [doi]
• Low-Power Driven Logic Synthesis Using Accurate Power Estimation TechniqueP. Patil, Tan-Li Chou, Kaushik Roy, R. Roy. 179-184 [doi]
• Dynamic Power Management for Microprocessors: A Case StudyVivek Tiwari, Ryan Donnelly, Sharad Malik, Ricardo González. 185-192 [doi]
• Low-Power Design by Hazard FilteringVishwani D. Agrawal. 193-197 [doi]
• Low-Power Configurable Processor Array for DLMS Adaptive FilteringS. Ramanathan, V. Visvanathan. 198-207 [doi]
• Industrial Strength Formal Verification Techniques for Hardware DesignsS. P. Rajan, Natarajan Shankar, Mandayam K. Srivas. 208-212 [doi]
• Formal Verification of Digital SystemsGitanjali Swamy. 213-217 [doi]
• Formal Verification of Combinational CircuitJawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli. 218-225 [doi]
• Inductive Verification of Sequential Circuits with a DatapathI. Chakrabarti, Dilip Sarkar, Arun K. Majumdar. 226-231 [doi]
• Some Recent Advances in Software and Hardware Logic SimulationRajeev Murgai, Masahiro Fujita. 232-238 [doi]
• Multiobjective Search Based Algorithms for Circuit Partitioning Problem for Acceleration of Logic SimulationS. Harikumer, S. Kumar. 239-243 [doi]
• Media ProcessorsSunil Nanda. 244-246 [doi]
• A Parallel Architecture for Video CompressionPartha Sarathi Bhattacharjee, Sajal K. Das, Debashis Saha, D. Roychowdhury, Parimal Pal Chaudhuri. 247-252 [doi]
• Design of a VLSI Hardware PET DecoderGiuseppe Ascia, Vincenzo Catania, Giuseppe Ficili. 253-256 [doi]
• A Scalable Memory System DesignGab Joong Jeong, Kyoung Hwan Kwon, Moon Key Lee, Seung Han An. 257-260 [doi]
• Energy-Efficiency of VLSI Caches: A Comparative StudyMilind B. Kamble, Kanad Ghose. 261-267 [doi]
• Behavioral Array Mapping into Multiport Memories Targeting Low PowerPreeti Ranjan Panda, Nikil D. Dutt. 268-273 [doi]
• Sequential Circuit Testing: From DFT to SFTRichard M. Chou, Kewal K. Saluja. 274-278 [doi]
• Synthesis for Testability by Two-Clock ControlShashank K. Mehta, Kent L. Einspahr, Sharad C. Seth. 279-283 [doi]
• A Practical Method for Selecting Partial Scan Flip-flops for Large CircuitsSudipta Bhawmik, Indradeep Ghosh. 284-288 [doi]
• Optimizing Test Hardware for At-Speed Testing of Datapaths in an Integrated CircuitDebashis Bhattacharya, S. Freeman, W. Lin. 289-296 [doi]
• Efficient Implementation of Multiple On-Chip Signature CheckingMohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar. 297-302 [doi]
• New BIST Techniques for Universal and Robust Testing of CMOS Stuck-Open FaultsDebesh Kumar Das, Susanta Chakraborty, Bhargab B. Bhattacharya. 303-309 [doi]
• Developing A New Approach For Multimedia DesignWalden C. Rhines. 310-313 [doi]
• Design For Testability: Today And In The FutureTom Williams. 314-317 [doi]
• Asynchronous Design - An Interesting AlternativeKimberly D. Emerson. 318-321 [doi]
• Delay-Insensitive Carry-Lookahead AddersFu-Chiung Cheng, Stephen H. Unger, Michael Theobald, Wen-Chung Cho. 322-328 [doi]
• A Visual Approach for Asynchronous Circuit SynthesisRadhakrishna Nagalla, Graham R. Hellestrand. 329-335 [doi]
• An Asynchronous Morphological Processor for Multi-Media ApplicationsKamran Eshraghian, Juan A. Montiel-Nelson, Saeid Nooshabadi. 336-341 [doi]
• A New Methodology for the Design of Asynchronous Digital CircuitsK. Nanda, S. K. Desai, S. K. Roy. 342-347 [doi]
• Asynchronous Implementation of Synchronous Esterel SpecificationsRaj S. Mitra, Bishnupriya Bhattacharya, Luciano Lavagno. 348-355 [doi]
• Reconfigurable ComputingDinesh Bhatia. 356-359 [doi]
• A General Reconfiguration Technique for Fault Tolerant Processor ArchitecturesEshwar Belani, Ravi Mittal. 360-363 [doi]
• Design of t-UED/AUED Codes from Berger s AUED CodeGosta Pada Biswas, Idranil Sen Gupta. 364-369 [doi]
• A Novel Reconfigurable Co-Processor ArchitectureGaurav Aggarwal, Nitin Thaper, Kamal Aggarwal, M. Balakrishnan, Shashi Kumar. 370-375 [doi]
• Characterization and Implicit Identification of Sequential IndistinguishabilityVamsi Boppana, Ismed Hartanto, W. Kent Fuchs. 376-380 [doi]
• Distributed Diagnostic Simulation of Stuck-At Faults in Sequential CircuitsSrikanth Venkataraman, W. Kent Fuchs. 381-387 [doi]
• Design for Testability and Built-In Self-Test of Mixed-Signal Circuits: A TutorialAbhijit Chatterjee, Naveena Nagi. 388-392 [doi]
• Optimal Design of Checksum-Based Checkers for Fault Detection in Linear Analog CircuitsHeebyung Yoon, Abhijit Chatterjee, Joseph L. A. Hughes. 393-397 [doi]
• Pseudoduplication - An ACOB Technique for Single-Ended CircuitsBapiraju Vinnakota, Ramesh Harjani, Wooyoung Choi. 398-402 [doi]
• SYMPHONY: A Fast Mixed Signal Simulator for BiMOS Analog/Digital CircuitsPremal Buch, Ernest S. Kuh. 403-407 [doi]
• FLYER: Fast Fault Simulation of Linear Analog Circuits Using Polynomial Waveform and Perturbed State RepresentationPramodchandran N. Variyam, Abhijit Chatterjee. 408-412 [doi]
• FAMAS: FAult Modeling via Adaptive SimulationHaiming Jin, Ravishankar K. Iyer, Mei-Chen Hsueh. 413-419 [doi]
• Development of an Analogue MicroprocessorD. L. Grundy, M. Bozic, John V. Hatfield. 420-424 [doi]
• An Expert System Approach to Analog Circuit SynthesisV. Ravindra Babu, Baquer Mazhari, M. M. Hasan. 425-428 [doi]
• A Self-Biased High Performance Folded Cascode CMOS Op-AmpPradip Mandal, V. Visvanathan. 429-434 [doi]
• Tuning Schemes for Transmission Zeros of Continuous-Time FiltersK. Ravi Shankar, K. Radhakrishna Rao, Srinivasan Venkatraman. 435-438 [doi]
• Synthesis of Analog CMOS CircuitsK. Ravi Shanker, Vinita Vasudevan. 439-445 [doi]
• C3L: A Chip for Connected Component LabelingAshley Rasquinha, N. Ranganathan. 446-450 [doi]
• Micropipeline Architecture for Multiplier-less FIR FiltersSaeid Nooshabadi, Juan A. Montiel-Nelson, G. S. Visweswaran, D. Nagchoudhuri. 451-456 [doi]
• VLSI Implementation of Modulo Multiplication Using Carry Free AdditionPalash Sarkar, Bimal K. Roy, Pabitra Pal Choudhury. 457-460 [doi]
• The Design of A Digital IC for Thyristor TriggeringTales Cleber Pimenta, Luiz Lenarth G. Vermaas, Paulo César Crepaldi, Robson L. Moreno. 461-464 [doi]
• Architectures for Arithmetic over GF(2:::m:::)Rana Barua, Samik Sengupta. 465-469 [doi]
• On the Detection of Reset Faults in Synchronous Sequential CircuitsIrith Pomeranz, Sudhakar M. Reddy. 470-474 [doi]
• Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test GenerationDilip Krishnaswamy, Michael S. Hsiao, Vikram Saxena, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee. 475-481 [doi]
• Faster Fault Simulation Through Distributed ComputingC. P. Ravikumar, Vikas Jain, Anurag Dod. 482-487 [doi]
• Deriving Signal Constraints to Accelerate Sequential Test GenerationSrimat T. Chakradhar, Vijay Gangaram, Steven G. Rothweiler. 488-494 [doi]
• Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault SimulationElizabeth M. Rudnick, Janak H. Patel. 495-503 [doi]
• Interconnection Delay and Clock Cycle Selection in High Level SynthesisHortensia Mecha, Milagros Fernández. 504-505 [doi]
• Shake And Bake: A Method of Mapping Code to Irregular DSPsThomas Charles Wilson, Gary William Grewal. 506-508 [doi]
• A Simulation Methodology for Software Energy EvaluationHuzefa Mehta, Robert Michael Owens, Mary Jane Irwin. 509-510 [doi]
• Pseudo Kronecker Expressions for Symmetric FunctionsRolf Drechsler. 511-513 [doi]
• Adder and Comparator Synthesis with Exclusive-OR Transform of InputsJames Jacob, P. Srinivas Sivakumar, Vishwani D. Agrawal. 514-515 [doi]
• A Method for Synthesizing Area Efficient Multilevel PTL CircuitsSubir Bandyopadhyay, Arunita Jaekel, Graham A. Jullien. 516-519 [doi]
• Shift Switching with Domino Logic: Asynchronous VLSI Comparator SchemesRon Lin. 520-522 [doi]
• FPGA Implementation of Median FilterR. Maheshwari, S. S. S. P. Rao, E. G. Poonach. 523-524 [doi]
• A 2.5 V 10 bit SAR ADCSubhashish Mukherjee, C. Srinivasan, Vivek Pawar, Sumeet Mathur, Kiran Godbole, Eric Soenen. 525-526 [doi]
• Parallel Decoder for Cellular Automata Based Byte Error Correcting CodeSantanu Chattopadhyay, Parimal Pal Chaudhuri. 527-528 [doi]
• A Design Technique of TSC Checker for Borden s CodeGosta Pada Biswas, Indranil Sengupta. 529-530 [doi]
• An Algorithm for Finding a Non-Trivial Lower Bound for Channel RoutingRajat K. Pal, Sudebkumar Prasant Pal, Ajit Pal. 531-533 [doi]
• On Full Reset as a Design-For-Testability TechniqueIrith Pomeranz, Sudhakar M. Reddy. 534-536 [doi]
• Impact of Partial Reset on Fault Independent Testing and BISTHuy Nguyen, Abhijit Chatterjee, Rabindra K. Roy. 537-539 [doi]
• A Novel Hierarchical Test Generation Method for ProcessorsRaghuram S. Tupuri, Jacob A. Abraham. 540-541 [doi]
• Dynamic Fault Grouping for PROOFS: A Win for Large Sequential CircuitsCharles R. Graham, Elizabeth M. Rudnick, Janak H. Patel. 542-544 [doi]
• Input Pattern Classification for Detection of Stuck-ON and Bridging Faults Using I/sub DDQ/ Testing in BiCMOS and CMOS CircuitsSankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana. 545-546 [doi]
• On Incorporation of BIST for the Synthesis of Easily and Fully Testable ControllersChunduri Rama Mohan, S. Mitra, Partha Pal Chaudhuri. 547-563 [doi]