Debashis Bhattacharya - researchr alias

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Viewing Publication 1 - 22 from 22

2005

Transistor-Level Optimization of Digital Designs with Flex CellsRob Roy, Debashis Bhattacharya, Vamsi Boppana. Computer, 38(2):53-61, 2005. [doi]

1999

Instruction-Driven Wake-Up Mechanisms for Snoopy TAP ControllerDebashis Bhattacharya. vts 1999: 467-472 [doi]

1998

Hierarchical Test Access Architecture for Embedded Cores in an Integrated CircuitDebashis Bhattacharya. vts 1998: 8-14 [doi]

1997

1995

Test Generation for Path Delay Faults Using Binary Decision DiagramsDebashis Bhattacharya, Prathima Agrawal, Vishwani D. Agrawal. TC, 44(3):434-447, 1995.

An efficient method for generating exhaustive test setsTed Stanion, Debashis Bhattacharya, Carl Sechen. tcad, 14(12):1516-1525, 1995. [doi]

A three-stage partial scan design method to ease ATPGShang-E Tai, Debashis Bhattacharya. et, 7(1-2):95-104, 1995. [doi]

1994

A Three-Stage Partial Scan Design Method Using the Sequential Circuit Flow GraphShang-E Tai, Debashis Bhattacharya. vlsid 1994: 101-106

1993

Boolean algebraic test generation using a distributed systemDebashis Bhattacharya, Prathima Agrawal. iccad 1993: 440-443 [doi]

Architecture of a Min-Max Simulator on MARSKumar N. Lalgudi, Debashis Bhattacharya, Prathima Agrawal. vlsid 1993: 246-249

Pipelined Fault Simulation on Parallel Machines Using the Circuit Flow GraphShang-E Tai, Debashis Bhattacharya. iccd 1993: 564-567

1992

Delay Fault Test Generation for Scan/Hold Circuits Using Boolean ExpressionsDebashis Bhattacharya, Prathima Agrawal, Vishwani D. Agrawal. dac 1992: 159-164 [doi]

1991

TSUNAMI: A Path Oriented Scheme for Algebraic Test GenerationTed Stanion, Debashis Bhattacharya. ftcs 1991: 36-43

1990

CMP3F: a high speed fault simulator for the Connection MachineAjit Agrawal, Debashis Bhattacharya. itc 1990: 410-416 [doi]

Binary to Quaternary Encoding in Clocked CMOS Circuits Using Weak BufferDebashis Bhattacharya. ismvl 1990: 174-180

Designing for high-level test generationDebashis Bhattacharya, John P. Hayes. tcad, 9(7):752-766, 1990. [doi]

A hierarchical test generation methodology for digital circuitsDebashis Bhattacharya, John P. Hayes. et, 1(2):103-123, 1990. [doi]

1989

High-Level Test Generation for VLSIDebashis Bhattacharya, Brian T. Murray, John P. Hayes. Computer, 22(4):16-24, 1989.

1988

Hierarchical modeling and test generation for digital circuitsDebashis Bhattacharya. PhD thesis, University of Michigan, USA, 1988. [doi]

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